Searched refs:sclk_low (Results 1 – 2 of 2) sorted by relevance
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()410 if (current_state->sclk_low == current_state->sclk_high) in rs780_force_fbdiv()436 (new_state->sclk_low == old_state->sclk_low)) in rs780_set_engine_clock_scaling()440 new_state->sclk_low, false, &min_dividers); in rs780_set_engine_clock_scaling()483 (new_state->sclk_low == old_state->sclk_low)) in rs780_set_engine_clock_spc()501 (new_state->sclk_low == old_state->sclk_low)) in rs780_activate_engine_clk_scaling()504 if (new_state->sclk_high == new_state->sclk_low) in rs780_activate_engine_clk_scaling()757 ps->sclk_low = sclk; in rs780_parse_pplib_clock_info()783 ps->sclk_low = rdev->clock.default_sclk; in rs780_parse_pplib_clock_info()948 ps->sclk_low, ps->min_voltage); in rs780_dpm_print_power_state()[all …]
55 u32 sclk_low; member
