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Searched refs:rtw_write32_set (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.10/drivers/net/wireless/realtek/rtw88/
Drtw8821c.c146 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8821c_phy_set_param()
355 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
611 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
614 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
615 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
666 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); in rtw8821c_coex_cfg_init()
667 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); in rtw8821c_coex_cfg_init()
706 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); in rtw8821c_coex_cfg_ant_switch()
728 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); in rtw8821c_coex_cfg_ant_switch()
739 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL); in rtw8821c_coex_cfg_ant_switch()
[all …]
Drtw8822c.c69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); in rtw8822c_header_file_init()
70 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); in rtw8822c_header_file_init()
71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); in rtw8822c_header_file_init()
72 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); in rtw8822c_header_file_init()
77 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); in rtw8822c_header_file_init()
708 rtw_write32_set(rtwdev, 0x1830, BIT(30)); in rtw8822c_dac_cal_backup()
709 rtw_write32_set(rtwdev, 0x4130, BIT(30)); in rtw8822c_dac_cal_backup()
721 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); in rtw8822c_dac_cal_restore_dck()
727 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); in rtw8822c_dac_cal_restore_dck()
733 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); in rtw8822c_dac_cal_restore_dck()
[all …]
Drtw8822b.c143 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); in rtw8822b_phy_set_param()
155 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); in rtw8822b_phy_set_param()
650 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8822b_set_channel_bb()
1078 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1081 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1082 rtw_write32_set(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1129 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); in rtw8822b_coex_cfg_init()
1130 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); in rtw8822b_coex_cfg_init()
Dmac.c78 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN); in rtw_mac_pre_system_cfg()
1084 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); in __priority_queue_cfg()
1123 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); in __priority_queue_cfg_legacy()
1253 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); in rtw_drv_info_cfg()
Dhci.h132 static inline void rtw_write32_set(struct rtw_dev *rtwdev, u32 addr, u32 bit) in rtw_write32_set() function
Dbf.c367 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER); in rtw_bf_phy_init()
Drtw8723d.c158 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); in rtw8723d_phy_set_param()
160 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); in rtw8723d_phy_set_param()
162 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); in rtw8723d_phy_set_param()
1515 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); in rtw8723d_coex_cfg_init()
1516 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); in rtw8723d_coex_cfg_init()
Dwow.c273 rtw_write32_set(rtwdev, REG_RXPKT_NUM, BIT_RW_RELEASE); in rtw_wow_rx_dma_stop()
Dpci.c481 rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR, in rtw_pci_reset_buf_desc()
531 rtw_write32_set(rtwdev, RTK_PCI_CTRL, in rtw_pci_dma_reset()
Dmac80211.c389 rtw_write32_set(rtwdev, REG_FWHW_TXQ_CTRL, in rtw_ops_bss_info_changed()
Dfw.c1117 rtw_write32_set(rtwdev, REG_DWBCN0_CTRL, BIT_BCN_VALID); in rtw_fw_write_data_rsvd_page()
Dcoex.c768 rtw_write32_set(rtwdev, REG_SYS_SDIO_CTRL, BIT_LTE_MUX_CTRL_PATH); in rtw_coex_coex_ctrl_owner()