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Searched refs:res_pool (Results 1 – 25 of 46) sorted by relevance

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/Linux-v5.10/drivers/bus/fsl-mc/
Dfsl-mc-allocator.c37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c95 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
190 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
228 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
229 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
233 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
246 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
268 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
282 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
297 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
298 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
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Ddcn30_resource.c1457 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1476 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1593 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1858 const struct resource_pool *pool = dc->res_pool; in dcn30_split_stream_for_mpc_or_odm()
1916 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1933 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
1964 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); in dcn30_internal_validate_bw()
2025 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2045 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_internal_validate_bw()
2066 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn30_internal_validate_bw()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c68 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
70 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
72 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
118 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
122 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
126 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
144 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
148 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
152 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
297 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
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Ddcn20_resource.c1673 const struct resource_pool *pool = dc->res_pool; in dcn20_acquire_dsc()
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1761 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1869 const struct resource_pool *pool = dc->res_pool; in dcn20_split_stream_for_odm()
1972 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
2011 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2031 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2050 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2386 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2432 for (i = 0; i < dc->res_pool->pipe_count; i++) {
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c77 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
94 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
135 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
159 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
274 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
661 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
681 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
690 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
691 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
718 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) in dcn10_bios_golden_init()
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Ddcn10_hw_sequencer_debug.c80 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
84 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
112 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
118 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
190 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
232 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
289 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
329 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
384 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
415 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc.c727 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version); in dc_construct()
728 if (!dc->res_pool) in dc_construct()
731 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
740 if (dc->res_pool->funcs->update_bw_bounding_box) in dc_construct()
741 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in dc_construct()
787 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
812 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
854 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
875 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { in disable_vbios_mode_if_required()
876 if (dc->res_pool->stream_enc[j]->id == enc_inst) { in disable_vbios_mode_if_required()
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Ddc_resource.c146 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
151 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
155 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
159 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
164 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
168 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
172 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
176 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
180 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
186 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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Ddc_stream.c424 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
444 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
455 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
677 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { in dc_stream_add_dsc_to_resource()
678 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); in dc_stream_add_dsc_to_resource()
Ddc_debug.c314 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in context_timing_trace()
318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
Ddc_surface.c150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
Ddc_link.c440 &link->dc->res_pool->audio_support; in link_detect_sink()
848 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in dc_link_detect_helper()
1390 if (link->dc->res_pool->funcs->link_init) in dc_link_construct()
1391 link->dc->res_pool->funcs->link_init(link); in dc_link_construct()
1461 if (link->dc->res_pool->funcs->panel_cntl_create && in dc_link_construct()
1467 link->dc->res_pool->funcs->panel_cntl_create( in dc_link_construct()
1488 link->dc->res_pool->funcs->link_enc_create(&enc_init_data); in dc_link_construct()
2563 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_set_psr_allow_active()
2564 struct dmub_psr *psr = dc->res_pool->psr; in dc_link_set_psr_allow_active()
2581 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_get_psr_state()
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Ddc_link_hwss.c100 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_enable_link_phy()
105 link->dc->res_pool->dp_clock_source; in dp_enable_link_phy()
226 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_disable_link_phy()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c206 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1510 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { in power_down_encoders()
1511 dc->res_pool->stream_enc[i]->funcs->dp_blank( in power_down_encoders()
1512 dc->res_pool->stream_enc[i]); in power_down_encoders()
1537 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1538 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1539 dc->res_pool->timing_generators[i]); in power_down_controllers()
1547 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1548 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1551 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hwseq.c83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
167 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
184 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
205 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
/Linux-v5.10/drivers/gpu/drm/amd/display/modules/power/
Dpower_helpers.c660 bool dmub_init_abm_config(struct resource_pool *res_pool, in dmub_init_abm_config() argument
669 if (res_pool->abm == NULL && res_pool->multiple_abms[0] == NULL) in dmub_init_abm_config()
672 if (res_pool->abm == NULL) in dmub_init_abm_config()
716 if (res_pool->multiple_abms[0]) { in dmub_init_abm_config()
717 result = res_pool->multiple_abms[0]->funcs->init_abm_config( in dmub_init_abm_config()
718 res_pool->multiple_abms[0], (char *)(&config), sizeof(struct abm_config_table)); in dmub_init_abm_config()
721 result = res_pool->abm->funcs->init_abm_config( in dmub_init_abm_config()
722 res_pool->abm, (char *)(&config), sizeof(struct abm_config_table)); in dmub_init_abm_config()
Dpower_helpers.h50 bool dmub_init_abm_config(struct resource_pool *res_pool,
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c57 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce60_should_enable_fbc()
70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c76 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_clock()
129 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_dispclk()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
158 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
176 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
177 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_vbios_smu.c127 struct dmcu *dmcu = dc->res_pool->dmcu; in rv1_vbios_smu_set_dispclk()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.c123 struct dmcu *dmcu = dc->res_pool->dmcu; in rn_vbios_smu_set_dispclk()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_aux.c441 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_configure_timeout()
563 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_transfer_raw()

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