Searched refs:read_aux_reg (Results 1 – 17 of 17) sorted by relevance
491 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()500 unsigned int val = read_aux_reg(ctl); in __before_dc_op()528 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) in __after_dc_op()564 write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS); in __dc_disable()571 write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS); in __dc_enable()612 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ in __ic_entire_inv()689 ctrl = read_aux_reg(ARC_REG_SLC_CTRL); in slc_op_rgn()721 read_aux_reg(ARC_REG_SLC_CTRL); in slc_op_rgn()723 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); in slc_op_rgn()748 ctrl = read_aux_reg(ARC_REG_SLC_CTRL); in slc_op_line()[all …]
136 idx = read_aux_reg(ARC_REG_TLBINDEX); in utlb_invalidate()157 idx = read_aux_reg(ARC_REG_TLBINDEX); in tlb_entry_lkup()541 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff; in create_tlb()738 tmp = read_aux_reg(ARC_REG_MMU_BCR); in read_decode_mmu_bcr()909 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()972 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff; in tlb_paranoid_check()
11 #define read_aux_reg(r) __builtin_arc_lr(r) macro18 static inline int read_aux_reg(u32 r) in read_aux_reg() function37 tmp = read_aux_reg(reg); \
130 return read_aux_reg(ARC_REG_MCIP_READBACK); in __mcip_cmd_read()
80 l = read_aux_reg(ARC_REG_MCIP_READBACK); in arc_read_gfrc()83 h = read_aux_reg(ARC_REG_MCIP_READBACK); in arc_read_gfrc()140 l = read_aux_reg(AUX_RTC_LOW); in arc_read_rtc()141 h = read_aux_reg(AUX_RTC_HIGH); in arc_read_rtc()142 status = read_aux_reg(AUX_RTC_CTRL); in arc_read_rtc()198 return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); in arc_read_timer1()
144 enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); in nps_clkevent_rm_thread()147 thread = read_aux_reg(CTOP_AUX_THREAD_ID); in nps_clkevent_rm_thread()169 thread = read_aux_reg(CTOP_AUX_THREAD_ID); in nps_clkevent_add_thread()170 enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); in nps_clkevent_add_thread()
110 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_read_counter()112 result = (u64) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32; in arc_pmu_read_counter()113 result |= read_aux_reg(ARC_REG_PCT_SNAPL); in arc_pmu_read_counter()231 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_enable()239 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_disable()307 read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx)); in arc_pmu_start()327 read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx)); in arc_pmu_stop()410 active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT); in arc_pmu_intr()431 read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx)); in arc_pmu_intr()617 cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0)); in arc_pmu_device_probe()[all …]
47 ienb = read_aux_reg(AUX_IENABLE); in arc_init_IRQ()68 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_mask()77 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_unmask()
72 save->ctrl = read_aux_reg(ARC_REG_FPU_CTRL); in fpu_save_restore()73 save->status = read_aux_reg(ARC_REG_FPU_STATUS); in fpu_save_restore()
44 gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_update_gfrc_halt_mask()64 mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_update_debug_halt_mask()117 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_ipi_send()139 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ in mcip_ipi_clear()
87 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); in read_decode_ccm_bcr()101 region = read_aux_reg(ARC_REG_AUX_ICCM); in read_decode_ccm_bcr()111 region = read_aux_reg(ARC_REG_AUX_DCCM); in read_decode_ccm_bcr()182 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); in read_arc_build_cfg_regs()325 ctl = read_aux_reg(ARC_REG_LPB_CTRL); in arc_cpu_mumbojumbo()
93 tmp = read_aux_reg(ARC_REG_STATUS32); in arc_init_IRQ()
61 ienb = read_aux_reg(AUX_IENABLE); in nps400_irq_mask()71 ienb = read_aux_reg(AUX_IENABLE); in nps400_irq_unmask()
80 unsigned int irqact = read_aux_reg(AUX_IRQ_ACT); in arch_local_irq_enable()
337 pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \
69 #define read_aux_reg(r) 0 macro
313 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; in axs103_early_init()
