Searched refs:pwr_state (Results 1 – 9 of 9) sorted by relevance
116 enum vga_switcheroo_state pwr_state; member304 client->pwr_state = VGA_SWITCHEROO_ON; in register_client()464 return client->pwr_state; in vga_switcheroo_pwr_state()680 client->pwr_state = VGA_SWITCHEROO_ON; in vga_switchon()692 client->pwr_state = VGA_SWITCHEROO_OFF; in vga_switchoff()806 if (client->pwr_state == VGA_SWITCHEROO_ON) in vga_switcheroo_debugfs_write()818 if (client->pwr_state == VGA_SWITCHEROO_OFF) in vga_switcheroo_debugfs_write()
103 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()129 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()136 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_update_clocks()141 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in rn_update_clocks()144 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in rn_update_clocks()420 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in rn_init_clocks()
1580 u32 pwr_state = 0, io_level = 0; in sdhci_msm_handle_pwr_irq() local1615 pwr_state = REQ_BUS_ON; in sdhci_msm_handle_pwr_irq()1619 pwr_state = REQ_BUS_OFF; in sdhci_msm_handle_pwr_irq()1623 if (pwr_state) { in sdhci_msm_handle_pwr_irq()1627 pwr_state & REQ_BUS_ON); in sdhci_msm_handle_pwr_irq()1630 pwr_state & REQ_BUS_ON); in sdhci_msm_handle_pwr_irq()1647 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()1699 if (pwr_state) in sdhci_msm_handle_pwr_irq()1700 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
105 int pwr_state; member823 (chip->pwr_state == US_SUSPEND)) { in rts51x_invoke_transport()883 chip->pwr_state = US_RESUME; in realtek_cr_autosuspend_setup()
1802 u8 pwr_state; in wl3501_get_power() local1806 &pwr_state, sizeof(pwr_state)); in wl3501_get_power()1809 wrqu->power.disabled = !pwr_state; in wl3501_get_power()
734 u32 pwr_state = cdns_torrent_dp_read(regmap, in cdns_torrent_dp_set_a0_pll() local740 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << in cdns_torrent_dp_set_a0_pll()746 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << in cdns_torrent_dp_set_a0_pll()753 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << in cdns_torrent_dp_set_a0_pll()755 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << in cdns_torrent_dp_set_a0_pll()761 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); in cdns_torrent_dp_set_a0_pll()
1367 __u8 pwr_state) in cec_msg_report_power_status() argument1371 msg->msg[2] = pwr_state; in cec_msg_report_power_status()1375 __u8 *pwr_state) in cec_ops_report_power_status() argument1377 *pwr_state = msg->msg[2]; in cec_ops_report_power_status()
733 hda_nid_t nid, unsigned int pwr_state) in hdac_hdmi_set_power_state() argument739 if (!snd_hdac_check_power_state(hdev, nid, pwr_state)) { in hdac_hdmi_set_power_state()743 pwr_state); in hdac_hdmi_set_power_state()745 nid, pwr_state); in hdac_hdmi_set_power_state()
351 enum dcn_pwr_state pwr_state; member
