1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
7
8 #include <asm/bug.h>
9 #include <asm/proc-fns.h>
10
11 #include <asm/memory.h>
12 #include <asm/mte.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
16
17 /*
18 * VMALLOC range.
19 *
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
22 * and fixed mappings
23 */
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
26
27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
28
29 #define FIRST_USER_ADDRESS 0UL
30
31 #ifndef __ASSEMBLY__
32
33 #include <asm/cmpxchg.h>
34 #include <asm/fixmap.h>
35 #include <linux/mmdebug.h>
36 #include <linux/mm_types.h>
37 #include <linux/sched.h>
38
39 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
40 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
41
42 /* Set stride and tlb_level in flush_*_tlb_range */
43 #define flush_pmd_tlb_range(vma, addr, end) \
44 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
45 #define flush_pud_tlb_range(vma, addr, end) \
46 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
47 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
48
49 /*
50 * Outside of a few very special situations (e.g. hibernation), we always
51 * use broadcast TLB invalidation instructions, therefore a spurious page
52 * fault on one CPU which has been handled concurrently by another CPU
53 * does not need to perform additional invalidation.
54 */
55 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
56
57 /*
58 * ZERO_PAGE is a global shared page that is always zero: used
59 * for zero-mapped memory areas etc..
60 */
61 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
62 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
63
64 #define pte_ERROR(e) \
65 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
66
67 /*
68 * Macros to convert between a physical address and its placement in a
69 * page table entry, taking care of 52-bit addresses.
70 */
71 #ifdef CONFIG_ARM64_PA_BITS_52
72 #define __pte_to_phys(pte) \
73 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
74 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
75 #else
76 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
77 #define __phys_to_pte_val(phys) (phys)
78 #endif
79
80 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
81 #define pfn_pte(pfn,prot) \
82 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
83
84 #define pte_none(pte) (!pte_val(pte))
85 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
86 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
87
88 /*
89 * The following only work if pte_present(). Undefined behaviour otherwise.
90 */
91 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
92 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
93 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
94 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
95 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
96 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
97 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
98 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
99 PTE_ATTRINDX(MT_NORMAL_TAGGED))
100
101 #define pte_cont_addr_end(addr, end) \
102 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
103 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
104 })
105
106 #define pmd_cont_addr_end(addr, end) \
107 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
108 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
109 })
110
111 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
112 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
113 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
114
115 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
116 #define pte_valid_not_user(pte) \
117 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
118 #define pte_valid_user(pte) \
119 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
120
121 /*
122 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
123 * so that we don't erroneously return false for pages that have been
124 * remapped as PROT_NONE but are yet to be flushed from the TLB.
125 * Note that we can't make any assumptions based on the state of the access
126 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
127 * TLB.
128 */
129 #define pte_accessible(mm, pte) \
130 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
131
132 /*
133 * p??_access_permitted() is true for valid user mappings (subject to the
134 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
135 * set.
136 */
137 #define pte_access_permitted(pte, write) \
138 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
139 #define pmd_access_permitted(pmd, write) \
140 (pte_access_permitted(pmd_pte(pmd), (write)))
141 #define pud_access_permitted(pud, write) \
142 (pte_access_permitted(pud_pte(pud), (write)))
143
clear_pte_bit(pte_t pte,pgprot_t prot)144 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
145 {
146 pte_val(pte) &= ~pgprot_val(prot);
147 return pte;
148 }
149
set_pte_bit(pte_t pte,pgprot_t prot)150 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
151 {
152 pte_val(pte) |= pgprot_val(prot);
153 return pte;
154 }
155
clear_pmd_bit(pmd_t pmd,pgprot_t prot)156 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
157 {
158 pmd_val(pmd) &= ~pgprot_val(prot);
159 return pmd;
160 }
161
set_pmd_bit(pmd_t pmd,pgprot_t prot)162 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
163 {
164 pmd_val(pmd) |= pgprot_val(prot);
165 return pmd;
166 }
167
pte_mkwrite(pte_t pte)168 static inline pte_t pte_mkwrite(pte_t pte)
169 {
170 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
171 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
172 return pte;
173 }
174
pte_mkclean(pte_t pte)175 static inline pte_t pte_mkclean(pte_t pte)
176 {
177 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
178 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
179
180 return pte;
181 }
182
pte_mkdirty(pte_t pte)183 static inline pte_t pte_mkdirty(pte_t pte)
184 {
185 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
186
187 if (pte_write(pte))
188 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
189
190 return pte;
191 }
192
pte_wrprotect(pte_t pte)193 static inline pte_t pte_wrprotect(pte_t pte)
194 {
195 /*
196 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
197 * clear), set the PTE_DIRTY bit.
198 */
199 if (pte_hw_dirty(pte))
200 pte = pte_mkdirty(pte);
201
202 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
203 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
204 return pte;
205 }
206
pte_mkold(pte_t pte)207 static inline pte_t pte_mkold(pte_t pte)
208 {
209 return clear_pte_bit(pte, __pgprot(PTE_AF));
210 }
211
pte_mkyoung(pte_t pte)212 static inline pte_t pte_mkyoung(pte_t pte)
213 {
214 return set_pte_bit(pte, __pgprot(PTE_AF));
215 }
216
pte_mkspecial(pte_t pte)217 static inline pte_t pte_mkspecial(pte_t pte)
218 {
219 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
220 }
221
pte_mkcont(pte_t pte)222 static inline pte_t pte_mkcont(pte_t pte)
223 {
224 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
225 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
226 }
227
pte_mknoncont(pte_t pte)228 static inline pte_t pte_mknoncont(pte_t pte)
229 {
230 return clear_pte_bit(pte, __pgprot(PTE_CONT));
231 }
232
pte_mkpresent(pte_t pte)233 static inline pte_t pte_mkpresent(pte_t pte)
234 {
235 return set_pte_bit(pte, __pgprot(PTE_VALID));
236 }
237
pmd_mkcont(pmd_t pmd)238 static inline pmd_t pmd_mkcont(pmd_t pmd)
239 {
240 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
241 }
242
pte_mkdevmap(pte_t pte)243 static inline pte_t pte_mkdevmap(pte_t pte)
244 {
245 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
246 }
247
set_pte(pte_t * ptep,pte_t pte)248 static inline void set_pte(pte_t *ptep, pte_t pte)
249 {
250 WRITE_ONCE(*ptep, pte);
251
252 /*
253 * Only if the new pte is valid and kernel, otherwise TLB maintenance
254 * or update_mmu_cache() have the necessary barriers.
255 */
256 if (pte_valid_not_user(pte)) {
257 dsb(ishst);
258 isb();
259 }
260 }
261
262 extern void __sync_icache_dcache(pte_t pteval);
263
264 /*
265 * PTE bits configuration in the presence of hardware Dirty Bit Management
266 * (PTE_WRITE == PTE_DBM):
267 *
268 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
269 * 0 0 | 1 0 0
270 * 0 1 | 1 1 0
271 * 1 0 | 1 0 1
272 * 1 1 | 0 1 x
273 *
274 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
275 * the page fault mechanism. Checking the dirty status of a pte becomes:
276 *
277 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
278 */
279
__check_racy_pte_update(struct mm_struct * mm,pte_t * ptep,pte_t pte)280 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
281 pte_t pte)
282 {
283 pte_t old_pte;
284
285 if (!IS_ENABLED(CONFIG_DEBUG_VM))
286 return;
287
288 old_pte = READ_ONCE(*ptep);
289
290 if (!pte_valid(old_pte) || !pte_valid(pte))
291 return;
292 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
293 return;
294
295 /*
296 * Check for potential race with hardware updates of the pte
297 * (ptep_set_access_flags safely changes valid ptes without going
298 * through an invalid entry).
299 */
300 VM_WARN_ONCE(!pte_young(pte),
301 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
302 __func__, pte_val(old_pte), pte_val(pte));
303 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
304 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
305 __func__, pte_val(old_pte), pte_val(pte));
306 }
307
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)308 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
309 pte_t *ptep, pte_t pte)
310 {
311 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
312 __sync_icache_dcache(pte);
313
314 if (system_supports_mte() &&
315 pte_present(pte) && pte_tagged(pte) && !pte_special(pte))
316 mte_sync_tags(ptep, pte);
317
318 __check_racy_pte_update(mm, ptep, pte);
319
320 set_pte(ptep, pte);
321 }
322
323 /*
324 * Huge pte definitions.
325 */
326 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
327
328 /*
329 * Hugetlb definitions.
330 */
331 #define HUGE_MAX_HSTATE 4
332 #define HPAGE_SHIFT PMD_SHIFT
333 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
334 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
335 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
336
pgd_pte(pgd_t pgd)337 static inline pte_t pgd_pte(pgd_t pgd)
338 {
339 return __pte(pgd_val(pgd));
340 }
341
p4d_pte(p4d_t p4d)342 static inline pte_t p4d_pte(p4d_t p4d)
343 {
344 return __pte(p4d_val(p4d));
345 }
346
pud_pte(pud_t pud)347 static inline pte_t pud_pte(pud_t pud)
348 {
349 return __pte(pud_val(pud));
350 }
351
pte_pud(pte_t pte)352 static inline pud_t pte_pud(pte_t pte)
353 {
354 return __pud(pte_val(pte));
355 }
356
pud_pmd(pud_t pud)357 static inline pmd_t pud_pmd(pud_t pud)
358 {
359 return __pmd(pud_val(pud));
360 }
361
pmd_pte(pmd_t pmd)362 static inline pte_t pmd_pte(pmd_t pmd)
363 {
364 return __pte(pmd_val(pmd));
365 }
366
pte_pmd(pte_t pte)367 static inline pmd_t pte_pmd(pte_t pte)
368 {
369 return __pmd(pte_val(pte));
370 }
371
mk_pud_sect_prot(pgprot_t prot)372 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
373 {
374 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
375 }
376
mk_pmd_sect_prot(pgprot_t prot)377 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
378 {
379 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
380 }
381
382 #ifdef CONFIG_NUMA_BALANCING
383 /*
384 * See the comment in include/linux/pgtable.h
385 */
pte_protnone(pte_t pte)386 static inline int pte_protnone(pte_t pte)
387 {
388 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
389 }
390
pmd_protnone(pmd_t pmd)391 static inline int pmd_protnone(pmd_t pmd)
392 {
393 return pte_protnone(pmd_pte(pmd));
394 }
395 #endif
396
397 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
398
pmd_present(pmd_t pmd)399 static inline int pmd_present(pmd_t pmd)
400 {
401 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
402 }
403
404 /*
405 * THP definitions.
406 */
407
408 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
pmd_trans_huge(pmd_t pmd)409 static inline int pmd_trans_huge(pmd_t pmd)
410 {
411 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
412 }
413 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
414
415 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
416 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
417 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
418 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
419 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
420 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
421 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
422 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
423 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
424
pmd_mkinvalid(pmd_t pmd)425 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
426 {
427 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
428 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
429
430 return pmd;
431 }
432
433 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
434
435 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
436
437 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
438
439 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
440 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
441 #endif
pmd_mkdevmap(pmd_t pmd)442 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
443 {
444 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
445 }
446
447 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
448 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
449 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
450 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
451 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
452
453 #define pud_young(pud) pte_young(pud_pte(pud))
454 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
455 #define pud_write(pud) pte_write(pud_pte(pud))
456
457 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
458
459 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
460 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
461 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
462 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
463
464 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
465
466 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
467 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
468
469 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
470 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
471
472 #define __pgprot_modify(prot,mask,bits) \
473 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
474
475 #define pgprot_nx(prot) \
476 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
477
478 /*
479 * Mark the prot value as uncacheable and unbufferable.
480 */
481 #define pgprot_noncached(prot) \
482 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
483 #define pgprot_writecombine(prot) \
484 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
485 #define pgprot_device(prot) \
486 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
487 /*
488 * DMA allocations for non-coherent devices use what the Arm architecture calls
489 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
490 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
491 * is intended for MMIO and thus forbids speculation, preserves access size,
492 * requires strict alignment and can also force write responses to come from the
493 * endpoint.
494 */
495 #define pgprot_dmacoherent(prot) \
496 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
497 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
498
499 #define __HAVE_PHYS_MEM_ACCESS_PROT
500 struct file;
501 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
502 unsigned long size, pgprot_t vma_prot);
503
504 #define pmd_none(pmd) (!pmd_val(pmd))
505
506 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
507
508 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
509 PMD_TYPE_TABLE)
510 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
511 PMD_TYPE_SECT)
512 #define pmd_leaf(pmd) pmd_sect(pmd)
513
514 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
pud_sect(pud_t pud)515 static inline bool pud_sect(pud_t pud) { return false; }
pud_table(pud_t pud)516 static inline bool pud_table(pud_t pud) { return true; }
517 #else
518 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
519 PUD_TYPE_SECT)
520 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
521 PUD_TYPE_TABLE)
522 #endif
523
524 extern pgd_t init_pg_dir[PTRS_PER_PGD];
525 extern pgd_t init_pg_end[];
526 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
527 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
528 extern pgd_t idmap_pg_end[];
529 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
530
531 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
532
in_swapper_pgdir(void * addr)533 static inline bool in_swapper_pgdir(void *addr)
534 {
535 return ((unsigned long)addr & PAGE_MASK) ==
536 ((unsigned long)swapper_pg_dir & PAGE_MASK);
537 }
538
set_pmd(pmd_t * pmdp,pmd_t pmd)539 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
540 {
541 #ifdef __PAGETABLE_PMD_FOLDED
542 if (in_swapper_pgdir(pmdp)) {
543 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
544 return;
545 }
546 #endif /* __PAGETABLE_PMD_FOLDED */
547
548 WRITE_ONCE(*pmdp, pmd);
549
550 if (pmd_valid(pmd)) {
551 dsb(ishst);
552 isb();
553 }
554 }
555
pmd_clear(pmd_t * pmdp)556 static inline void pmd_clear(pmd_t *pmdp)
557 {
558 set_pmd(pmdp, __pmd(0));
559 }
560
pmd_page_paddr(pmd_t pmd)561 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
562 {
563 return __pmd_to_phys(pmd);
564 }
565
pmd_page_vaddr(pmd_t pmd)566 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
567 {
568 return (unsigned long)__va(pmd_page_paddr(pmd));
569 }
570
571 /* Find an entry in the third-level page table. */
572 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
573
574 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
575 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
576 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
577
578 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
579
580 /* use ONLY for statically allocated translation tables */
581 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
582
583 /*
584 * Conversion functions: convert a page and protection to a page entry,
585 * and a page entry and page directory to the page they refer to.
586 */
587 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
588
589 #if CONFIG_PGTABLE_LEVELS > 2
590
591 #define pmd_ERROR(e) \
592 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
593
594 #define pud_none(pud) (!pud_val(pud))
595 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
596 #define pud_present(pud) pte_present(pud_pte(pud))
597 #define pud_leaf(pud) pud_sect(pud)
598 #define pud_valid(pud) pte_valid(pud_pte(pud))
599
set_pud(pud_t * pudp,pud_t pud)600 static inline void set_pud(pud_t *pudp, pud_t pud)
601 {
602 #ifdef __PAGETABLE_PUD_FOLDED
603 if (in_swapper_pgdir(pudp)) {
604 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
605 return;
606 }
607 #endif /* __PAGETABLE_PUD_FOLDED */
608
609 WRITE_ONCE(*pudp, pud);
610
611 if (pud_valid(pud)) {
612 dsb(ishst);
613 isb();
614 }
615 }
616
pud_clear(pud_t * pudp)617 static inline void pud_clear(pud_t *pudp)
618 {
619 set_pud(pudp, __pud(0));
620 }
621
pud_page_paddr(pud_t pud)622 static inline phys_addr_t pud_page_paddr(pud_t pud)
623 {
624 return __pud_to_phys(pud);
625 }
626
pud_page_vaddr(pud_t pud)627 static inline unsigned long pud_page_vaddr(pud_t pud)
628 {
629 return (unsigned long)__va(pud_page_paddr(pud));
630 }
631
632 /* Find an entry in the second-level page table. */
633 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
634
635 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
636 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
637 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
638
639 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
640
641 /* use ONLY for statically allocated translation tables */
642 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
643
644 #else
645
646 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
647
648 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
649 #define pmd_set_fixmap(addr) NULL
650 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
651 #define pmd_clear_fixmap()
652
653 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
654
655 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
656
657 #if CONFIG_PGTABLE_LEVELS > 3
658
659 #define pud_ERROR(e) \
660 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
661
662 #define p4d_none(p4d) (!p4d_val(p4d))
663 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
664 #define p4d_present(p4d) (p4d_val(p4d))
665
set_p4d(p4d_t * p4dp,p4d_t p4d)666 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
667 {
668 if (in_swapper_pgdir(p4dp)) {
669 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
670 return;
671 }
672
673 WRITE_ONCE(*p4dp, p4d);
674 dsb(ishst);
675 isb();
676 }
677
p4d_clear(p4d_t * p4dp)678 static inline void p4d_clear(p4d_t *p4dp)
679 {
680 set_p4d(p4dp, __p4d(0));
681 }
682
p4d_page_paddr(p4d_t p4d)683 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
684 {
685 return __p4d_to_phys(p4d);
686 }
687
p4d_page_vaddr(p4d_t p4d)688 static inline unsigned long p4d_page_vaddr(p4d_t p4d)
689 {
690 return (unsigned long)__va(p4d_page_paddr(p4d));
691 }
692
693 /* Find an entry in the frst-level page table. */
694 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
695
696 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
697 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
698 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
699
700 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
701
702 /* use ONLY for statically allocated translation tables */
703 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
704
705 #else
706
707 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
708 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
709
710 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
711 #define pud_set_fixmap(addr) NULL
712 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
713 #define pud_clear_fixmap()
714
715 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
716
717 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
718
719 #define pgd_ERROR(e) \
720 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
721
722 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
723 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
724
pte_modify(pte_t pte,pgprot_t newprot)725 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
726 {
727 /*
728 * Normal and Normal-Tagged are two different memory types and indices
729 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
730 */
731 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
732 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
733 PTE_ATTRINDX_MASK;
734 /* preserve the hardware dirty information */
735 if (pte_hw_dirty(pte))
736 pte = pte_mkdirty(pte);
737 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
738 return pte;
739 }
740
pmd_modify(pmd_t pmd,pgprot_t newprot)741 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
742 {
743 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
744 }
745
746 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
747 extern int ptep_set_access_flags(struct vm_area_struct *vma,
748 unsigned long address, pte_t *ptep,
749 pte_t entry, int dirty);
750
751 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
752 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)753 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
754 unsigned long address, pmd_t *pmdp,
755 pmd_t entry, int dirty)
756 {
757 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
758 }
759
pud_devmap(pud_t pud)760 static inline int pud_devmap(pud_t pud)
761 {
762 return 0;
763 }
764
pgd_devmap(pgd_t pgd)765 static inline int pgd_devmap(pgd_t pgd)
766 {
767 return 0;
768 }
769 #endif
770
771 /*
772 * Atomic pte/pmd modifications.
773 */
774 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(pte_t * ptep)775 static inline int __ptep_test_and_clear_young(pte_t *ptep)
776 {
777 pte_t old_pte, pte;
778
779 pte = READ_ONCE(*ptep);
780 do {
781 old_pte = pte;
782 pte = pte_mkold(pte);
783 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
784 pte_val(old_pte), pte_val(pte));
785 } while (pte_val(pte) != pte_val(old_pte));
786
787 return pte_young(pte);
788 }
789
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)790 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
791 unsigned long address,
792 pte_t *ptep)
793 {
794 return __ptep_test_and_clear_young(ptep);
795 }
796
797 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)798 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
799 unsigned long address, pte_t *ptep)
800 {
801 int young = ptep_test_and_clear_young(vma, address, ptep);
802
803 if (young) {
804 /*
805 * We can elide the trailing DSB here since the worst that can
806 * happen is that a CPU continues to use the young entry in its
807 * TLB and we mistakenly reclaim the associated page. The
808 * window for such an event is bounded by the next
809 * context-switch, which provides a DSB to complete the TLB
810 * invalidation.
811 */
812 flush_tlb_page_nosync(vma, address);
813 }
814
815 return young;
816 }
817
818 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
819 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)820 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
821 unsigned long address,
822 pmd_t *pmdp)
823 {
824 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
825 }
826 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
827
828 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)829 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
830 unsigned long address, pte_t *ptep)
831 {
832 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
833 }
834
835 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
836 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)837 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
838 unsigned long address, pmd_t *pmdp)
839 {
840 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
841 }
842 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
843
844 /*
845 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
846 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
847 */
848 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)849 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
850 {
851 pte_t old_pte, pte;
852
853 pte = READ_ONCE(*ptep);
854 do {
855 old_pte = pte;
856 pte = pte_wrprotect(pte);
857 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
858 pte_val(old_pte), pte_val(pte));
859 } while (pte_val(pte) != pte_val(old_pte));
860 }
861
862 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
863 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)864 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
865 unsigned long address, pmd_t *pmdp)
866 {
867 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
868 }
869
870 #define pmdp_establish pmdp_establish
pmdp_establish(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t pmd)871 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
872 unsigned long address, pmd_t *pmdp, pmd_t pmd)
873 {
874 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
875 }
876 #endif
877
878 /*
879 * Encode and decode a swap entry:
880 * bits 0-1: present (must be zero)
881 * bits 2-7: swap type
882 * bits 8-57: swap offset
883 * bit 58: PTE_PROT_NONE (must be zero)
884 */
885 #define __SWP_TYPE_SHIFT 2
886 #define __SWP_TYPE_BITS 6
887 #define __SWP_OFFSET_BITS 50
888 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
889 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
890 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
891
892 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
893 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
894 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
895
896 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
897 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
898
899 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
900 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
901 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
902 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
903
904 /*
905 * Ensure that there are not more swap files than can be encoded in the kernel
906 * PTEs.
907 */
908 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
909
910 extern int kern_addr_valid(unsigned long addr);
911
912 #ifdef CONFIG_ARM64_MTE
913
914 #define __HAVE_ARCH_PREPARE_TO_SWAP
arch_prepare_to_swap(struct page * page)915 static inline int arch_prepare_to_swap(struct page *page)
916 {
917 if (system_supports_mte())
918 return mte_save_tags(page);
919 return 0;
920 }
921
922 #define __HAVE_ARCH_SWAP_INVALIDATE
arch_swap_invalidate_page(int type,pgoff_t offset)923 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
924 {
925 if (system_supports_mte())
926 mte_invalidate_tags(type, offset);
927 }
928
arch_swap_invalidate_area(int type)929 static inline void arch_swap_invalidate_area(int type)
930 {
931 if (system_supports_mte())
932 mte_invalidate_tags_area(type);
933 }
934
935 #define __HAVE_ARCH_SWAP_RESTORE
arch_swap_restore(swp_entry_t entry,struct page * page)936 static inline void arch_swap_restore(swp_entry_t entry, struct page *page)
937 {
938 if (system_supports_mte() && mte_restore_tags(entry, page))
939 set_bit(PG_mte_tagged, &page->flags);
940 }
941
942 #endif /* CONFIG_ARM64_MTE */
943
944 /*
945 * On AArch64, the cache coherency is handled via the set_pte_at() function.
946 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)947 static inline void update_mmu_cache(struct vm_area_struct *vma,
948 unsigned long addr, pte_t *ptep)
949 {
950 /*
951 * We don't do anything here, so there's a very small chance of
952 * us retaking a user fault which we just fixed up. The alternative
953 * is doing a dsb(ishst), but that penalises the fastpath.
954 */
955 }
956
957 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
958
959 #ifdef CONFIG_ARM64_PA_BITS_52
960 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
961 #else
962 #define phys_to_ttbr(addr) (addr)
963 #endif
964
965 /*
966 * On arm64 without hardware Access Flag, copying from user will fail because
967 * the pte is old and cannot be marked young. So we always end up with zeroed
968 * page after fork() + CoW for pfn mappings. We don't always have a
969 * hardware-managed access flag on arm64.
970 */
arch_faults_on_old_pte(void)971 static inline bool arch_faults_on_old_pte(void)
972 {
973 WARN_ON(preemptible());
974
975 return !cpu_has_hw_af();
976 }
977 #define arch_faults_on_old_pte arch_faults_on_old_pte
978
979 #endif /* !__ASSEMBLY__ */
980
981 #endif /* __ASM_PGTABLE_H */
982
