Searched refs:pll_in_use (Results 1 – 6 of 6) sorted by relevance
1739 u32 pll_in_use = 0; in radeon_get_pll_use_mask() local1747 pll_in_use |= (1 << test_radeon_crtc->pll_id); in radeon_get_pll_use_mask()1749 return pll_in_use; in radeon_get_pll_use_mask()1881 u32 pll_in_use; in radeon_atom_pick_pll() local1905 pll_in_use = radeon_get_pll_use_mask(crtc); in radeon_atom_pick_pll()1906 if (!(pll_in_use & (1 << ATOM_PPLL2))) in radeon_atom_pick_pll()1908 if (!(pll_in_use & (1 << ATOM_PPLL1))) in radeon_atom_pick_pll()1914 pll_in_use = radeon_get_pll_use_mask(crtc); in radeon_atom_pick_pll()1915 if (!(pll_in_use & (1 << ATOM_PPLL2))) in radeon_atom_pick_pll()1917 if (!(pll_in_use & (1 << ATOM_PPLL1))) in radeon_atom_pick_pll()[all …]
265 u32 pll_in_use = 0; in amdgpu_pll_get_use_mask() local273 pll_in_use |= (1 << test_amdgpu_crtc->pll_id); in amdgpu_pll_get_use_mask()275 return pll_in_use; in amdgpu_pll_get_use_mask()
2144 u32 pll_in_use; in dce_v8_0_pick_pll() local2167 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v8_0_pick_pll()2168 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v8_0_pick_pll()2170 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v8_0_pick_pll()2176 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v8_0_pick_pll()2177 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v8_0_pick_pll()2179 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v8_0_pick_pll()2181 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v8_0_pick_pll()
2287 u32 pll_in_use; in dce_v11_0_pick_pll() local2344 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v11_0_pick_pll()2346 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v11_0_pick_pll()2348 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v11_0_pick_pll()2353 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v11_0_pick_pll()2355 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v11_0_pick_pll()2357 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v11_0_pick_pll()
2254 u32 pll_in_use; in dce_v10_0_pick_pll() local2275 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v10_0_pick_pll()2276 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v10_0_pick_pll()2278 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v10_0_pick_pll()2280 if (!(pll_in_use & (1 << ATOM_PPLL0))) in dce_v10_0_pick_pll()
2152 u32 pll_in_use; in dce_v6_0_pick_pll() local2169 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v6_0_pick_pll()2170 if (!(pll_in_use & (1 << ATOM_PPLL2))) in dce_v6_0_pick_pll()2172 if (!(pll_in_use & (1 << ATOM_PPLL1))) in dce_v6_0_pick_pll()
