| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1670 int pipe_idx) in dcn20_acquire_dsc() argument
1674 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1681 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1682 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1868 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1873 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1874 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1875 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1876 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1877 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
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| D | dcn20_resource.h | 144 int pipe_idx);
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| D | dcn20_hwseq.c | 611 pipe_ctx->pipe_idx); in dcn20_disable_plane()
1263 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) in dcn20_detect_pipe_changes()
1687 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); in dcn20_program_front_end_for_ctx()
2186 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); in dcn20_reset_back_end_for_pipe()
2240 *color = pipe_colors[top_pipe->pipe_idx]; in dcn20_get_mpctree_visual_confirm_color()
2475 pipe_ctx->pipe_idx = i; in dcn20_fpga_init_hw()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 966 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
977 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
978 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
979 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
980 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
981 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
982 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1124 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1199 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1245 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_30.h | 62 const unsigned int pipe_idx,
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 815 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
823 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
824 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
825 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
826 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
827 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
828 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
968 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1050 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1099 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_21.h | 66 const unsigned int pipe_idx,
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
769 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params() argument
777 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20_rq_dlg_get_dlg_params()
778 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20_rq_dlg_get_dlg_params()
779 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
780 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
781 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20_rq_dlg_get_dlg_params()
782 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
922 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1010 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
769 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params() argument
777 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20v2_rq_dlg_get_dlg_params()
778 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20v2_rq_dlg_get_dlg_params()
779 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
780 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
781 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20v2_rq_dlg_get_dlg_params()
782 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
922 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1011 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.h | 66 const unsigned int pipe_idx,
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| D | display_rq_dlg_calc_20v2.h | 66 const unsigned int pipe_idx,
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc() argument
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1857 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1862 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1863 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1864 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1865 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1866 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1867 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1868 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1880 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1882 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); in dcn30_split_stream_for_mpc_or_odm()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 1209 pipe_ctx->pipe_idx, in resource_build_scaling_params()
1293 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe()
1296 secondary_pipe->pipe_idx = preferred_pipe_idx; in find_idle_secondary_pipe()
1308 secondary_pipe->pipe_idx = i; in find_idle_secondary_pipe()
1408 split_pipe->pipe_idx = i; in acquire_first_split_pipe()
1461 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); in dc_add_plane_to_context() local
1462 if (pipe_idx >= 0) in dc_add_plane_to_context()
1463 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; in dc_add_plane_to_context()
1777 pipe_ctx->pipe_idx = i; in acquire_first_free_pipe()
2052 pipe_ctx->pipe_idx = tg_inst; in acquire_resource_from_hw_enabled_state()
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| D | dc_debug.c | 323 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) in context_timing_trace()
333 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) in context_timing_trace()
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| D | dc.c | 1483 int pipe_idx; in dc_acquire_release_mpc_3dlut() local
1493 for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { in dc_acquire_release_mpc_3dlut()
1494 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { in dc_acquire_release_mpc_3dlut()
1496 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; in dc_acquire_release_mpc_3dlut()
1549 context->res_ctx.pipe_ctx[i].pipe_idx = i; in dc_post_update_surfaces_to_stream()
1600 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; in dc_copy_state()
1603 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; in dc_copy_state()
1606 cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; in dc_copy_state()
1609 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; in dc_copy_state()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_lib.h | 54 const unsigned int pipe_idx,
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 148 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
240 pp_display_cfg->disp_configs[0].pipe_idx; in dce11_pplib_apply_display_requirements()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 310 input->src.hsplit_grp = pipe->pipe_idx; in pipe_ctx_to_e2e_pipe_params()
526 int pipe_idx = secondary_pipe->pipe_idx; in split_stream_across_pipes() local
533 secondary_pipe->pipe_idx = pipe_idx; in split_stream_across_pipes()
534 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
535 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
536 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
537 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
538 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()
539 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 1350 pipe_ctx[pipe_ctx->pipe_idx]; in dce110_enable_stream_timing()
1589 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1859 uint32_t *pipe_idx) in should_enable_fbc() argument
1886 if (pipe_ctx->pipe_idx != underlay_idx) { in should_enable_fbc()
1887 *pipe_idx = i; in should_enable_fbc()
1925 uint32_t pipe_idx = 0; in enable_fbc() local
1927 if (should_enable_fbc(dc, context, &pipe_idx)) { in enable_fbc()
1931 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in enable_fbc()
2615 pipe_ctx->pipe_idx, in dce110_program_front_end_for_pipe()
2636 pipe_ctx->pipe_idx, in dce110_program_front_end_for_pipe()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1096 int pipe_cnt, i, pipe_idx; in dcn21_calculate_wm() local
1105 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1114 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn21_calculate_wm()
1115 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn21_calculate_wm()
1117 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; in dcn21_calculate_wm()
1120 pipe_idx++; in dcn21_calculate_wm()
1133 if (pipe_cnt != pipe_idx) { in dcn21_calculate_wm()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/ |
| D | dm_services_types.h | 126 uint8_t pipe_idx; member
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| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_amdkfd_gfx_v9.c | 734 int pipe_idx; in get_wave_count() local
745 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; in get_wave_count()
747 soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0); in get_wave_count()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 319 uint8_t pipe_idx; member
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| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 1172 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1173 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1174 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1175 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
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