| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 787 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
812 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
854 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
950 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1019 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1022 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1045 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1048 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1055 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1068 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
[all …]
|
| D | dc_surface.c | 150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
|
| D | dc_debug.c | 318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
|
| D | dc_resource.c | 1293 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe()
1305 for (i = pool->pipe_count - 1; i >= 0; i--) { in find_idle_secondary_pipe()
1363 for (i = pool->pipe_count - 1; i >= 0; i--) { in acquire_free_pipe_for_head()
1389 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
1517 for (i = pool->pipe_count - 1; i >= 0; i--) { in dc_remove_plane_from_context()
1764 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_free_pipe()
2214 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_validate_global_state()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
|
| D | dcn10_hw_sequencer.c | 94 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
164 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
196 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
221 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
253 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
286 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
328 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
690 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
734 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
761 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
[all …]
|
| D | dcn10_resource.c | 986 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1412 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1415 pool->base.pipe_count = 3; in dcn10_resource_construct()
1573 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1642 pool->base.pipe_count = j; in dcn10_resource_construct()
1648 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1649 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1671 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 805 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
878 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1039 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1101 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1158 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1236 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1298 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1355 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1429 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
[all …]
|
| D | dce60_hw_sequencer.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 810 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
883 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
969 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1048 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1110 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1167 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1245 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1307 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1364 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1438 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
[all …]
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 823 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
986 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1274 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1275 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1276 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1277 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1278 pool->pipe_count++; in underlay_create()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1372 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1444 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
[all …]
|
| D | dce110_hw_sequencer.c | 1583 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
1877 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
1893 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
2040 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2065 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2066 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2115 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2140 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2443 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2471 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
[all …]
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1483 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1972 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
2011 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2031 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2432 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2478 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2547 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2570 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2592 for (i = 0; i < dc->res_pool->pipe_count; i++) {
[all …]
|
| D | dcn20_hwseq.c | 1429 int opp_count = dc->res_pool->pipe_count; in dcn20_update_dchubp_dpp()
1646 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1657 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1670 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1675 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1683 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1694 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1722 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1732 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1817 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_update_bandwidth()
[all …]
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1233 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1314 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1348 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1350 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1373 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1375 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1457 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1476 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1593 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1828 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
[all …]
|
| D | dcn30_hwseq.c | 396 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { in dcn30_program_all_writeback_pipes_in_tree()
601 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_init_hw()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 762 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
849 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1079 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1142 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 932 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
1105 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1184 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth()
1399 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; in update_bw_bounding_box()
1807 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1858 pool->base.pipe_count = 4; in dcn21_resource_construct()
1961 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
2029 pool->base.pipe_count = j; in dcn21_resource_construct()
2073 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 607 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
1077 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1164 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_construct()
1240 pool->base.pipe_count = j; in dce120_resource_construct()
1255 dc->caps.max_planes = pool->base.pipe_count; in dce120_resource_construct()
|
| /Linux-v5.10/sound/pci/mixart/ |
| D | mixart_core.h | 232 u32 pipe_count; /* set to 1 for instance */ member
394 u32 pipe_count; /* set to 1 (array size !) */ member
|
| D | mixart.c | 101 group_state.pipe_count = 1; in mixart_set_pipe_state()
124 group_state.pipe_count = 0; /* in case of start same command once again with pipe_count=0 */ in mixart_set_pipe_state()
567 stream_param.pipe_count = 1; /* set to 1 */ in mixart_set_format()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 783 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_destruct()
906 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1239 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1324 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_construct()
1393 dc->caps.max_planes = pool->base.pipe_count; in dce112_resource_construct()
|
| /Linux-v5.10/kernel/rcu/ |
| D | rcutorture.c | 1357 int pipe_count; in rcu_torture_one_read() local
1384 pipe_count = READ_ONCE(p->rtort_pipe_count); in rcu_torture_one_read()
1385 if (pipe_count > RCU_TORTURE_PIPE_LEN) { in rcu_torture_one_read()
1387 pipe_count = RCU_TORTURE_PIPE_LEN; in rcu_torture_one_read()
1390 if (pipe_count > 1) { in rcu_torture_one_read()
1395 __this_cpu_inc(rcu_torture_count[pipe_count]); in rcu_torture_one_read()
1410 if ((pipe_count > 1 || completed > 1) && !xchg(&err_segs_recorded, 1)) { in rcu_torture_one_read()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 166 for (i = 0; i < dc->res_pool->pipe_count; i++) { in ramp_up_dispclk_with_dpp()
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 208 unsigned int pipe_count; member
|
