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Searched refs:pipe_config (Results 1 – 25 of 45) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_dp_mst.c96 struct intel_crtc_state *pipe_config, in intel_dp_mst_compute_config() argument
107 &pipe_config->hw.adjusted_mode; in intel_dp_mst_compute_config()
114 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dp_mst_compute_config()
115 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
118 pipe_config->has_audio = connector->port->has_audio; in intel_dp_mst_compute_config()
120 pipe_config->has_audio = in intel_dp_mst_compute_config()
133 limits.min_bpp = intel_dp_min_bpp(pipe_config); in intel_dp_mst_compute_config()
142 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
144 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); in intel_dp_mst_compute_config()
146 ret = intel_dp_mst_compute_link_config(encoder, pipe_config, in intel_dp_mst_compute_config()
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Dintel_hdmi.c269 const struct intel_crtc_state *pipe_config) in g4x_infoframes_enabled() argument
345 const struct intel_crtc_state *pipe_config) in ibx_infoframes_enabled() argument
348 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in ibx_infoframes_enabled()
427 const struct intel_crtc_state *pipe_config) in cpt_infoframes_enabled() argument
430 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in cpt_infoframes_enabled()
504 const struct intel_crtc_state *pipe_config) in vlv_infoframes_enabled() argument
507 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in vlv_infoframes_enabled()
576 const struct intel_crtc_state *pipe_config) in hsw_infoframes_enabled() argument
580 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
1850 struct intel_crtc_state *pipe_config) in intel_hdmi_get_config() argument
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Dintel_lvds.c119 struct intel_crtc_state *pipe_config) in intel_lvds_get_config() argument
125 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
137 pipe_config->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
140 pipe_config->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
147 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
150 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
225 const struct intel_crtc_state *pipe_config, in intel_pre_enable_lvds() argument
230 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_pre_enable_lvds()
231 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_pre_enable_lvds()
238 pipe_config->shared_dpll); in intel_pre_enable_lvds()
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Dintel_display.c150 struct intel_crtc_state *pipe_config);
152 struct intel_crtc_state *pipe_config);
167 const struct intel_crtc_state *pipe_config);
169 const struct intel_crtc_state *pipe_config);
246 const struct intel_crtc_state *pipe_config) in intel_fdi_link_freq() argument
249 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
1399 const struct intel_crtc_state *pipe_config) in _vlv_enable_pll() argument
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1413 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); in vlv_enable_pll()
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Dintel_crt.c130 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
132 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
134 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
136 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
140 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
144 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
146 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
150 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
152 pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); in hsw_crt_get_config()
381 struct intel_crtc_state *pipe_config, in intel_crt_compute_config() argument
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Dintel_dvo.c163 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
169 pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); in intel_dvo_get_config()
181 pipe_config->hw.adjusted_mode.flags |= flags; in intel_dvo_get_config()
183 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
203 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
212 &pipe_config->hw.mode, in intel_enable_dvo()
213 &pipe_config->hw.adjusted_mode); in intel_enable_dvo()
252 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
258 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dvo_compute_config()
272 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dvo_compute_config()
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Dintel_dp.c1839 struct intel_crtc_state *pipe_config) in intel_dp_set_clock() argument
1861 if (pipe_config->port_clock == divisor[i].clock) { in intel_dp_set_clock()
1862 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
1863 pipe_config->clock_set = true; in intel_dp_set_clock()
1947 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_fec() argument
1955 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) in intel_dp_source_supports_fec()
1962 const struct intel_crtc_state *pipe_config) in intel_dp_supports_fec() argument
1964 return intel_dp_source_supports_fec(intel_dp, pipe_config) && in intel_dp_supports_fec()
2063 struct intel_crtc_state *pipe_config, in intel_dp_adjust_compliance_config() argument
2073 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
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Dicl_dsi.c275 const struct intel_crtc_state *pipe_config) in configure_dual_link_mode() argument
288 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
663 const struct intel_crtc_state *pipe_config) in gen11_dsi_configure_transcoder() argument
667 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
683 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { in gen11_dsi_configure_transcoder()
709 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
779 configure_dual_link_mode(encoder, pipe_config); in gen11_dsi_configure_transcoder()
1173 const struct intel_crtc_state *pipe_config, in gen11_dsi_pre_enable() argument
1177 gen11_dsi_map_pll(encoder, pipe_config); in gen11_dsi_pre_enable()
1180 gen11_dsi_enable_port_and_phy(encoder, pipe_config); in gen11_dsi_pre_enable()
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Dintel_ddi.c1542 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) in ddi_dotclock_get() argument
1546 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
1547 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1548 &pipe_config->fdi_m_n); in ddi_dotclock_get()
1549 else if (intel_crtc_has_dp_encoder(pipe_config)) in ddi_dotclock_get()
1550 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1551 &pipe_config->dp_m_n); in ddi_dotclock_get()
1552 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in ddi_dotclock_get()
1553 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
1555 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
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Dvlv_dsi.c263 struct intel_crtc_state *pipe_config, in intel_dsi_compute_config() argument
271 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
275 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
281 ret = intel_gmch_panel_fitting(pipe_config, conn_state); in intel_dsi_compute_config()
283 ret = intel_pch_panel_fitting(pipe_config, conn_state); in intel_dsi_compute_config()
295 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
297 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
301 pipe_config->mode_flags |= in intel_dsi_compute_config()
306 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
308 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
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Dintel_pipe_crc.c290 struct intel_crtc_state *pipe_config; in intel_crtc_crc_setup_workarounds() local
306 pipe_config = intel_atomic_get_crtc_state(state, crtc); in intel_crtc_crc_setup_workarounds()
307 if (IS_ERR(pipe_config)) { in intel_crtc_crc_setup_workarounds()
308 ret = PTR_ERR(pipe_config); in intel_crtc_crc_setup_workarounds()
312 pipe_config->uapi.mode_changed = pipe_config->has_psr; in intel_crtc_crc_setup_workarounds()
313 pipe_config->crc_enabled = enable; in intel_crtc_crc_setup_workarounds()
316 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
317 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_crtc_crc_setup_workarounds()
318 pipe_config->uapi.mode_changed = true; in intel_crtc_crc_setup_workarounds()
Dintel_sdvo.c1252 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1254 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); in i9xx_adjust_sdvo_tv_clock()
1255 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1256 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1279 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1302 struct intel_crtc_state *pipe_config, in intel_sdvo_compute_config() argument
1310 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_sdvo_compute_config()
1311 struct drm_display_mode *mode = &pipe_config->hw.mode; in intel_sdvo_compute_config()
1314 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
1315 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_sdvo_compute_config()
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Dintel_tv.c919 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
927 to_intel_crtc(pipe_config->uapi.crtc)->pipe); in intel_enable_tv()
1084 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
1088 &pipe_config->hw.adjusted_mode; in intel_tv_get_config()
1096 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); in intel_tv_get_config()
1118 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1161 pipe_config->mode_flags |= in intel_tv_get_config()
1183 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
1191 &pipe_config->hw.adjusted_mode; in intel_tv_compute_config()
1201 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_tv_compute_config()
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Dintel_vdsc.c381 struct intel_crtc_state *pipe_config) in intel_dsc_compute_params() argument
383 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
384 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
388 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
389 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; in intel_dsc_compute_params()
391 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
400 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
Dintel_vdsc.h20 struct intel_crtc_state *pipe_config);
Dintel_dp.h34 struct intel_crtc_state *pipe_config,
62 struct intel_crtc_state *pipe_config,
Dintel_lspcon.h34 const struct intel_crtc_state *pipe_config);
Dintel_hdmi.h32 struct intel_crtc_state *pipe_config,
Dintel_ddi.h39 struct intel_crtc_state *pipe_config);
/Linux-v5.10/drivers/usb/renesas_usbhs/
Dpipe.c477 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhsp_setup_pipebuff() local
489 buff_size = pipe_config->bufsize; in usbhsp_setup_pipebuff()
490 bufnmb = pipe_config->bufnum; in usbhsp_setup_pipebuff()
507 struct renesas_usbhs_driver_pipe_config *pipe_config = in usbhs_pipe_config_update() local
509 u16 dblb = pipe_config->double_buf ? DBLB : 0; in usbhs_pipe_config_update()
/Linux-v5.10/drivers/staging/media/atomisp/pci/runtime/binary/src/
Dbinary.c531 struct ia_css_pipe_config *pipe_config) /* [out] */ in isp2401_binary_get_shading_info_type_1() argument
548 assert(pipe_config); in isp2401_binary_get_shading_info_type_1()
666 pipe_config->internal_frame_origin_bqs_on_sctbl.x = (int32_t)internal_org_x_bqs_on_tbl; in isp2401_binary_get_shading_info_type_1()
667 pipe_config->internal_frame_origin_bqs_on_sctbl.y = (int32_t)internal_org_y_bqs_on_tbl; in isp2401_binary_get_shading_info_type_1()
685 pipe_config->internal_frame_origin_bqs_on_sctbl.x, in isp2401_binary_get_shading_info_type_1()
686 pipe_config->internal_frame_origin_bqs_on_sctbl.y); in isp2401_binary_get_shading_info_type_1()
699 struct ia_css_pipe_config *pipe_config) /* [out] */ in ia_css_binary_get_shading_info() argument
726 pipe_config); in ia_css_binary_get_shading_info()
/Linux-v5.10/drivers/staging/media/atomisp/pci/
Dia_css_pipe_public.h246 void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config);
Dsh_css_sp.c216 pipe->pipe_config = 0x0; /* No parameters */ in sh_css_sp_start_binary_copy()
290 pipe->pipe_config = in sh_css_sp_start_raw_copy()
293 pipe->pipe_config = pipe_conf_override; in sh_css_sp_start_raw_copy()
363 pipe->pipe_config = 0x0; /* No parameters */ in sh_css_sp_start_isys_copy()
1282 sh_css_sp_group.pipe[thread_id].pipe_config = in sh_css_sp_init_pipeline()
1289 sh_css_sp_group.pipe[thread_id].pipe_config = 0; in sh_css_sp_init_pipeline()
1368 sh_css_sp_group.pipe[thread_id].pipe_config |= (uint32_t) in sh_css_sp_init_pipeline()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c161 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
250 update->plane_info->tiling_info.gfx8.pipe_config, in update_surface_trace()
/Linux-v5.10/drivers/staging/media/atomisp/pci/runtime/binary/interface/
Dia_css_binary.h200 struct ia_css_pipe_config *pipe_config);

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