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Searched refs:phy_set_bb_reg (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/drivers/staging/rtl8188eu/hal/
Dodm_rtl8188e.c18 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); in dm_rx_hw_antena_div_init()
19 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); in dm_rx_hw_antena_div_init()
25 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, in dm_rx_hw_antena_div_init()
28 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); in dm_rx_hw_antena_div_init()
29 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); in dm_rx_hw_antena_div_init()
30 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); in dm_rx_hw_antena_div_init()
31 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); in dm_rx_hw_antena_div_init()
33 phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, in dm_rx_hw_antena_div_init()
36 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); in dm_rx_hw_antena_div_init()
37 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); in dm_rx_hw_antena_div_init()
[all …]
Dphy.c41 void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data) in phy_set_bb_reg() function
73 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord, in rf_serial_read()
77 phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2); in rf_serial_read()
105 phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr); in rf_serial_write()
228 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback()
229 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback()
232 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback()
233 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback()
237 phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand, in phy_set_bw_mode_callback()
239 phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00, in phy_set_bw_mode_callback()
[all …]
Drf_cfg.c230 phy_set_bb_reg(adapt, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); in rtl88eu_phy_rf_config()
233 phy_set_bb_reg(adapt, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in rtl88eu_phy_rf_config()
236 phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0); in rtl88eu_phy_rf_config()
239 phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0); in rtl88eu_phy_rf_config()
244 phy_set_bb_reg(adapt, pphyreg->rfintfs, BRFSI_RFENV, u4val); in rtl88eu_phy_rf_config()
Dodm.c298 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); in ODM_Write_DIG()
515 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ in odm_FalseAlarmCounterStatistics()
516 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ in odm_FalseAlarmCounterStatistics()
539 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); in odm_FalseAlarmCounterStatistics()
540 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); in odm_FalseAlarmCounterStatistics()
660 phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ in ODM_RF_Saving()
661 phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */ in ODM_RF_Saving()
662 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ in ODM_RF_Saving()
663 phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ in ODM_RF_Saving()
664 phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ in ODM_RF_Saving()
[all …]
Drf.c104 phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); in rtl88eu_phy_rf6052_set_cck_txpower()
106 phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); in rtl88eu_phy_rf6052_set_cck_txpower()
110 phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); in rtl88eu_phy_rf6052_set_cck_txpower()
112 phy_set_bb_reg(adapt, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); in rtl88eu_phy_rf6052_set_cck_txpower()
256 phy_set_bb_reg(adapt, regoffset, bMaskDWord, write_val); in write_ofdm_pwr_reg()
Dbb_cfg.c156 phy_set_bb_reg(adapt, v1, bMaskDWord, v2); in set_baseband_agc_config()
374 phy_set_bb_reg(adapt, addr, bMaskDWord, data); in rtl_bb_delay()
677 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, in rtl88eu_phy_bb_config()
Dusb_halinit.c588 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
589 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
601 phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01); in _InitAntenna_Selection()
/Linux-v5.10/drivers/staging/rtl8188eu/include/
Dphy.h13 void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data);