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Searched refs:pdiv (Results 1 – 25 of 43) sorted by relevance

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/Linux-v5.10/drivers/clk/tegra/
Dclk-tegra124.c153 { .pdiv = 1, .hw_val = 0 },
154 { .pdiv = 2, .hw_val = 1 },
155 { .pdiv = 3, .hw_val = 2 },
156 { .pdiv = 4, .hw_val = 3 },
157 { .pdiv = 5, .hw_val = 4 },
158 { .pdiv = 6, .hw_val = 5 },
159 { .pdiv = 8, .hw_val = 6 },
160 { .pdiv = 10, .hw_val = 7 },
161 { .pdiv = 12, .hw_val = 8 },
162 { .pdiv = 16, .hw_val = 9 },
[all …]
Dclk-tegra114.c149 { .pdiv = 1, .hw_val = 0 },
150 { .pdiv = 2, .hw_val = 1 },
151 { .pdiv = 3, .hw_val = 2 },
152 { .pdiv = 4, .hw_val = 3 },
153 { .pdiv = 5, .hw_val = 4 },
154 { .pdiv = 6, .hw_val = 5 },
155 { .pdiv = 8, .hw_val = 6 },
156 { .pdiv = 10, .hw_val = 7 },
157 { .pdiv = 12, .hw_val = 8 },
158 { .pdiv = 16, .hw_val = 9 },
[all …]
Dclk-tegra210.c1414 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); in tegra210_pllx_dyn_ramp()
1435 u32 pdiv; in tegra210_pll_fixed_mdiv_cfg() local
1442 p = params->round_p_to_pdiv(p, &pdiv); in tegra210_pll_fixed_mdiv_cfg()
1529 { .pdiv = 1, .hw_val = 0 },
1530 { .pdiv = 2, .hw_val = 1 },
1531 { .pdiv = 3, .hw_val = 2 },
1532 { .pdiv = 4, .hw_val = 3 },
1533 { .pdiv = 5, .hw_val = 4 },
1534 { .pdiv = 6, .hw_val = 5 },
1535 { .pdiv = 8, .hw_val = 6 },
[all …]
/Linux-v5.10/drivers/clk/samsung/
Dclk-pll.c109 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
114 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; in samsung_pll2126_recalc_rate()
118 do_div(fvco, (pdiv + 2) << sdiv); in samsung_pll2126_recalc_rate()
142 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
147 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; in samsung_pll3000_recalc_rate()
151 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
179 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
184 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; in samsung_pll35xx_recalc_rate()
188 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
201 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
Dclk-pll.h51 .pdiv = (_p), \
60 .pdiv = (_p), \
69 .pdiv = (_p), \
78 .pdiv = (_p), \
88 .pdiv = (_p), \
98 .pdiv = (_p), \
109 .pdiv = (_p), \
121 unsigned int pdiv; member
/Linux-v5.10/drivers/cpufreq/
Ds3c2412-cpufreq.c51 unsigned int hdiv, pdiv, armdiv, dvs; in s3c2412_cpufreq_calcdivs() local
99 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2412_cpufreq_calcdivs()
101 if ((hclk / pdiv) > cfg->max.pclk) in s3c2412_cpufreq_calcdivs()
102 pdiv++; in s3c2412_cpufreq_calcdivs()
104 cfg->freq.pclk = hclk / pdiv; in s3c2412_cpufreq_calcdivs()
106 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); in s3c2412_cpufreq_calcdivs()
108 if (pdiv > 2) in s3c2412_cpufreq_calcdivs()
111 pdiv *= hdiv; in s3c2412_cpufreq_calcdivs()
116 cfg->divs.p_divisor = pdiv * armdiv; in s3c2412_cpufreq_calcdivs()
Ds3c2440-cpufreq.c69 unsigned int hdiv, pdiv; in s3c2440_cpufreq_calcdivs() local
103 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2440_cpufreq_calcdivs()
105 if ((hclk / pdiv) > cfg->max.pclk) in s3c2440_cpufreq_calcdivs()
106 pdiv++; in s3c2440_cpufreq_calcdivs()
108 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); in s3c2440_cpufreq_calcdivs()
110 if (pdiv > 2) in s3c2440_cpufreq_calcdivs()
113 pdiv *= hdiv; in s3c2440_cpufreq_calcdivs()
134 cfg->divs.p_divisor = pdiv; in s3c2440_cpufreq_calcdivs()
Ds3c2410-cpufreq.c46 unsigned int hdiv, pdiv; in s3c2410_cpufreq_calcdivs() local
65 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
66 pclk = hclk / pdiv; in s3c2410_cpufreq_calcdivs()
73 pdiv *= hdiv; in s3c2410_cpufreq_calcdivs()
76 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
/Linux-v5.10/arch/arm/mach-s3c/
Dregs-s3c2443-clock.h153 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_mpll() local
157 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; in s3c2443_get_mpll()
161 pdiv &= S3C2443_PLLCON_PDIVMASK; in s3c2443_get_mpll()
165 do_div(fvco, pdiv << sdiv); in s3c2443_get_mpll()
173 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_epll() local
177 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; in s3c2443_get_epll()
181 pdiv &= S3C2443_PLLCON_PDIVMASK; in s3c2443_get_epll()
185 do_div(fvco, (pdiv + 2) << sdiv); in s3c2443_get_epll()
/Linux-v5.10/drivers/clk/
Dclk-cdce925.c68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ member
289 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) in cdce925_clk_set_pdiv() argument
295 0x03, (pdiv >> 8) & 0x03); in cdce925_clk_set_pdiv()
296 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
299 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
302 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); in cdce925_clk_set_pdiv()
305 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); in cdce925_clk_set_pdiv()
308 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); in cdce925_clk_set_pdiv()
311 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); in cdce925_clk_set_pdiv()
314 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); in cdce925_clk_set_pdiv()
[all …]
/Linux-v5.10/drivers/clk/bcm/
Dclk-iproc-pll.c114 vco_out->pdiv = 1; in pll_calc_param()
292 unsigned int pdiv; in pll_fractional_change_only() local
306 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_fractional_change_only()
307 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in pll_fractional_change_only()
309 if (pdiv != vco->pdiv) in pll_fractional_change_only()
331 if (vco->pdiv == 0) in pll_set_rate()
334 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
421 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_set_rate()
422 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); in pll_set_rate()
423 val |= vco->pdiv << ctrl->pdiv.shift; in pll_set_rate()
[all …]
Dclk-iproc-armpll.c202 unsigned int pdiv; in iproc_arm_pll_recalc_rate() local
218 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) & in iproc_arm_pll_recalc_rate()
220 if (pdiv == 0) in iproc_arm_pll_recalc_rate()
221 pdiv = 16; in iproc_arm_pll_recalc_rate()
230 pll->rate = (pll->rate / pdiv) / mdiv; in iproc_arm_pll_recalc_rate()
235 (unsigned int)(ndiv >> 20), pdiv, mdiv); in iproc_arm_pll_recalc_rate()
Dclk-sr.c43 .pdiv = REG_VAL(0x14, 0, 4),
103 .pdiv = REG_VAL(0x14, 0, 4),
162 .pdiv = REG_VAL(0x14, 0, 4),
197 .pdiv = REG_VAL(0x14, 0, 4),
251 .pdiv = REG_VAL(0x14, 0, 4),
287 .pdiv = REG_VAL(0x4, 26, 4),
332 .pdiv = REG_VAL(0x4, 26, 4),
371 .pdiv = REG_VAL(0x4, 26, 4),
Dclk-ns2.c47 .pdiv = REG_VAL(0x8, 0, 4),
110 .pdiv = REG_VAL(0x8, 0, 4),
172 .pdiv = REG_VAL(0x8, 0, 4),
234 .pdiv = REG_VAL(0x8, 0, 4),
Dclk-iproc.h98 unsigned int pdiv; member
174 struct iproc_clk_reg_op pdiv; member
Dclk-cygnus.c66 .pdiv = REG_VAL(0x14, 0, 4),
124 .pdiv = REG_VAL(0x4, 26, 4),
202 .pdiv = REG_VAL(0x14, 0, 4),
281 .pdiv = REG_VAL(0x44, 0, 4),
Dclk-nsp.c52 .pdiv = REG_VAL(0x18, 24, 3),
109 .pdiv = REG_VAL(0x4, 28, 3),
/Linux-v5.10/drivers/clk/imx/
Dclk-pll14xx.c122 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
127 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1416x_recalc_rate()
131 do_div(fvco, pdiv << sdiv); in clk_pll1416x_recalc_rate()
140 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; in clk_pll1443x_recalc_rate() local
147 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1443x_recalc_rate()
153 pdiv *= 65536; in clk_pll1443x_recalc_rate()
155 do_div(fvco, pdiv << sdiv); in clk_pll1443x_recalc_rate()
168 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; in clk_pll14xx_mp_change()
217 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
282 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/Linux-v5.10/drivers/thermal/tegra/
Dtegra124-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
Dtegra132-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
Dtegra210-soctherm.c52 .pdiv = 8,
71 .pdiv = 8,
90 .pdiv = 8,
107 .pdiv = 8,
Dsoctherm.h77 u32 pdiv, pdiv_ate, pdiv_mask; member
89 u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; member
/Linux-v5.10/drivers/clk/st/
Dclk-flexgen.c32 struct clk_divider pdiv; member
135 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
151 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
236 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
237 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
238 fgxbar->pdiv.width = 10; in clk_register_flexgen()
/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c1395 u32 pdiv; member
1420 params->pdiv = 0; in skl_wrpll_params_populate()
1423 params->pdiv = 1; in skl_wrpll_params_populate()
1426 params->pdiv = 2; in skl_wrpll_params_populate()
1429 params->pdiv = 4; in skl_wrpll_params_populate()
1567 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | in skl_ddi_hdmi_pll_dividers()
2458 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv, in cnl_wrpll_get_multipliers() argument
2464 *pdiv = 2; in cnl_wrpll_get_multipliers()
2468 *pdiv = 2; in cnl_wrpll_get_multipliers()
2472 *pdiv = 3; in cnl_wrpll_get_multipliers()
[all …]
/Linux-v5.10/arch/arm/mach-ep93xx/
Dclock.c360 int *psel, int *esel, int *pdiv, int *div) in calc_clk_div() argument
397 *pdiv = __pdiv - 3; in calc_clk_div()
417 int err, psel = 0, esel = 0, pdiv = 0, div = 0; in set_div_rate() local
420 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); in set_div_rate()
431 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; in set_div_rate()

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