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Searched refs:pcie_mlw_mask (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_device.c4730 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; in amdgpu_device_get_pcie_info()
4736 if (adev->pm.pcie_mlw_mask == 0) in amdgpu_device_get_pcie_info()
4737 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; in amdgpu_device_get_pcie_info()
4741 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) in amdgpu_device_get_pcie_info()
4793 if (adev->pm.pcie_mlw_mask == 0) { in amdgpu_device_get_pcie_info()
4795 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; in amdgpu_device_get_pcie_info()
4799 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | in amdgpu_device_get_pcie_info()
4808 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | in amdgpu_device_get_pcie_info()
4816 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | in amdgpu_device_get_pcie_info()
4823 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | in amdgpu_device_get_pcie_info()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c991 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) in smu_smc_hw_setup()
993 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) in smu_smc_hw_setup()
995 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) in smu_smc_hw_setup()
997 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) in smu_smc_hw_setup()
999 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) in smu_smc_hw_setup()
1001 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) in smu_smc_hw_setup()
/Linux-v5.10/drivers/gpu/drm/amd/pm/inc/
Damdgpu_dpm.h443 uint32_t pcie_mlw_mask; member
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_hwmgr.c847 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) in vega20_override_pcie_parameters()
849 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) in vega20_override_pcie_parameters()
851 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) in vega20_override_pcie_parameters()
853 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) in vega20_override_pcie_parameters()
855 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) in vega20_override_pcie_parameters()
857 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) in vega20_override_pcie_parameters()
Dsmu7_hwmgr.c2604 data->pcie_lane_cap = adev->pm.pcie_mlw_mask; in smu7_hwmgr_backend_init()