1 /******************************************************************************* 2 * 3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenFabrics.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 *******************************************************************************/ 34 35 #ifndef I40IW_VERBS_H 36 #define I40IW_VERBS_H 37 38 struct i40iw_ucontext { 39 struct ib_ucontext ibucontext; 40 struct i40iw_device *iwdev; 41 struct list_head cq_reg_mem_list; 42 spinlock_t cq_reg_mem_list_lock; /* memory list for cq's */ 43 struct list_head qp_reg_mem_list; 44 spinlock_t qp_reg_mem_list_lock; /* memory list for qp's */ 45 int abi_ver; 46 }; 47 48 struct i40iw_pd { 49 struct ib_pd ibpd; 50 struct i40iw_sc_pd sc_pd; 51 atomic_t usecount; 52 }; 53 54 struct i40iw_hmc_pble { 55 union { 56 u32 idx; 57 dma_addr_t addr; 58 }; 59 }; 60 61 struct i40iw_cq_mr { 62 struct i40iw_hmc_pble cq_pbl; 63 dma_addr_t shadow; 64 }; 65 66 struct i40iw_qp_mr { 67 struct i40iw_hmc_pble sq_pbl; 68 struct i40iw_hmc_pble rq_pbl; 69 dma_addr_t shadow; 70 struct page *sq_page; 71 }; 72 73 struct i40iw_pbl { 74 struct list_head list; 75 union { 76 struct i40iw_qp_mr qp_mr; 77 struct i40iw_cq_mr cq_mr; 78 }; 79 80 bool pbl_allocated; 81 bool on_list; 82 u64 user_base; 83 struct i40iw_pble_alloc pble_alloc; 84 struct i40iw_mr *iwmr; 85 }; 86 87 #define MAX_SAVE_PAGE_ADDRS 4 88 struct i40iw_mr { 89 union { 90 struct ib_mr ibmr; 91 struct ib_mw ibmw; 92 }; 93 struct ib_umem *region; 94 u16 type; 95 u32 page_cnt; 96 u64 page_size; 97 u32 npages; 98 u32 stag; 99 u64 length; 100 u64 pgaddrmem[MAX_SAVE_PAGE_ADDRS]; 101 struct i40iw_pbl iwpbl; 102 }; 103 104 struct i40iw_cq { 105 struct ib_cq ibcq; 106 struct i40iw_sc_cq sc_cq; 107 u16 cq_head; 108 u16 cq_size; 109 u16 cq_number; 110 bool user_mode; 111 u32 polled_completions; 112 u32 cq_mem_size; 113 struct i40iw_dma_mem kmem; 114 spinlock_t lock; /* for poll cq */ 115 struct i40iw_pbl *iwpbl; 116 }; 117 118 struct disconn_work { 119 struct work_struct work; 120 struct i40iw_qp *iwqp; 121 }; 122 123 struct iw_cm_id; 124 struct ietf_mpa_frame; 125 struct i40iw_ud_file; 126 127 struct i40iw_qp_kmode { 128 struct i40iw_dma_mem dma_mem; 129 u64 *wrid_mem; 130 }; 131 132 struct i40iw_qp { 133 struct ib_qp ibqp; 134 struct i40iw_sc_qp sc_qp; 135 struct i40iw_device *iwdev; 136 struct i40iw_cq *iwscq; 137 struct i40iw_cq *iwrcq; 138 struct i40iw_pd *iwpd; 139 struct i40iw_qp_host_ctx_info ctx_info; 140 struct i40iwarp_offload_info iwarp_info; 141 void *allocated_buffer; 142 refcount_t refcount; 143 struct iw_cm_id *cm_id; 144 void *cm_node; 145 struct ib_mr *lsmm_mr; 146 struct work_struct work; 147 enum ib_qp_state ibqp_state; 148 u32 iwarp_state; 149 u32 qp_mem_size; 150 u32 last_aeq; 151 atomic_t close_timer_started; 152 spinlock_t lock; /* for post work requests */ 153 struct i40iw_qp_context *iwqp_context; 154 void *pbl_vbase; 155 dma_addr_t pbl_pbase; 156 struct page *page; 157 u8 active_conn:1; 158 u8 user_mode:1; 159 u8 hte_added:1; 160 u8 flush_issued:1; 161 u8 destroyed:1; 162 u8 sig_all:1; 163 u8 pau_mode:1; 164 u8 rsvd:1; 165 u16 term_sq_flush_code; 166 u16 term_rq_flush_code; 167 u8 hw_iwarp_state; 168 u8 hw_tcp_state; 169 struct i40iw_qp_kmode kqp; 170 struct i40iw_dma_mem host_ctx; 171 struct timer_list terminate_timer; 172 struct i40iw_pbl iwpbl; 173 struct i40iw_dma_mem q2_ctx_mem; 174 struct i40iw_dma_mem ietf_mem; 175 struct completion sq_drained; 176 struct completion rq_drained; 177 struct completion free_qp; 178 }; 179 #endif 180
