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Searched refs:mmVGT_GSVS_RING_OFFSET_1_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h4102 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX … macro
Dgc_9_1_offset.h4332 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX … macro
Dgc_9_2_1_offset.h4286 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX … macro
Dgc_10_1_0_offset.h6476 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX … macro
Dgc_10_3_0_offset.h6105 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX … macro