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Searched refs:mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h91 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
Ddcn_1_0_offset.h391 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
Ddcn_2_0_0_offset.h35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
Ddcn_3_0_0_offset.h16 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h557 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … macro