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Searched refs:mmUVD_SCRATCH2 (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h46 #define mmUVD_SCRATCH2 macro
Dvcn_2_5_offset.h419 #define mmUVD_SCRATCH2 macro
Dvcn_2_0_0_offset.h404 #define mmUVD_SCRATCH2 macro
Dvcn_3_0_0_offset.h695 #define mmUVD_SCRATCH2 macro
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c923 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v1_0_start_spg_mode()
1081 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v1_0_start_dpg_mode()
1250 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v1_0_pause_dpg_mode()
1311 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v1_0_pause_dpg_mode()
1403 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v1_0_dec_ring_set_wptr()
Dvcn_v2_0.c912 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v2_0_start_dpg_mode()
1250 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v2_0_pause_dpg_mode()
1353 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v2_0_dec_ring_set_wptr()
Dvcn_v2_5.c894 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
Dvcn_v3_0.c1035 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v3_0_start_dpg_mode()