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Searched refs:mmUVD_POWER_STATUS (Results 1 – 17 of 17) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c721 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_disable_static_power_gating()
726 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_disable_static_power_gating()
735 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_enable_static_power_gating()
738 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_enable_static_power_gating()
963 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v1_0_start_dpg_mode()
966 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v1_0_start_dpg_mode()
1159 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1176 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1181 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, in vcn_v1_0_stop_dpg_mode()
1221 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
[all …]
Dvcn_v2_0.c737 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
743 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
755 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_enable_static_power_gating()
758 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
797 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v2_0_start_dpg_mode()
800 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v2_0_start_dpg_mode()
891 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
920 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
1103 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
[all …]
Dvcn_v2_5.c771 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
774 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
777 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
873 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
902 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
926 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
1302 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1315 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1319 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v2_5_stop_dpg_mode()
1382 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), in vcn_v2_5_stop()
[all …]
Dvcn_v3_0.c597 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
603 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_disable_static_power_gating()
612 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
615 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_enable_static_power_gating()
909 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v3_0_start_dpg_mode()
912 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v3_0_start_dpg_mode()
915 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v3_0_start_dpg_mode()
1015 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1042 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1442 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
[all …]
Duvd_v5_0.c299 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
Duvd_v6_0.c710 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v6_0_start()
1456 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); in uvd_v6_0_set_powergating_state()
Duvd_v7_0.c941 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, in uvd_v7_0_start()
1734 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_d.h91 #define mmUVD_POWER_STATUS 0x38fc macro
Duvd_4_0_d.h65 #define mmUVD_POWER_STATUS 0x38FC macro
Duvd_3_1_d.h93 #define mmUVD_POWER_STATUS 0x38fc macro
Duvd_5_0_d.h103 #define mmUVD_POWER_STATUS 0x38c4 macro
Duvd_6_0_d.h119 #define mmUVD_POWER_STATUS 0x38c4 macro
Duvd_7_0_offset.h28 #define mmUVD_POWER_STATUS … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h32 #define mmUVD_POWER_STATUS … macro
Dvcn_2_5_offset.h399 #define mmUVD_POWER_STATUS … macro
Dvcn_2_0_0_offset.h384 #define mmUVD_POWER_STATUS … macro
Dvcn_3_0_0_offset.h667 #define mmUVD_POWER_STATUS … macro