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Searched refs:mmUVD_CGC_CTRL (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c650 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
689 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
744 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
747 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
753 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
756 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
821 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
Duvd_v4_2.c584 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
587 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
593 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
596 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
607 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
623 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
Duvd_v3_1.c209 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
225 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm()
603 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
606 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
612 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
615 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
Duvd_v6_0.c1309 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1349 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1406 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1409 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1415 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1418 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1488 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
Dvcn_v1_0.c459 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
467 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
492 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
513 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
584 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
591 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
593 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
614 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
672 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_0.c490 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
497 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
522 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
543 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
620 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
651 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
658 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
660 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
681 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
Dvcn_v2_5.c553 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
560 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
588 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
609 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
687 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
718 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
725 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
727 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
747 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c664 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
671 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
699 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
720 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
820 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
848 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
855 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
857 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
878 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
Duvd_v7_0.c843 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
956 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1585 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1631 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
Duvd_3_1_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h308 #define mmUVD_CGC_CTRL … macro
Dvcn_2_5_offset.h501 #define mmUVD_CGC_CTRL … macro
Dvcn_2_0_0_offset.h508 #define mmUVD_CGC_CTRL … macro
Dvcn_3_0_0_offset.h817 #define mmUVD_CGC_CTRL … macro