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Searched refs:mmTA_CNTL_AUX (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c114 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
254 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
Dsi.c83 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
137 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
322 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
358 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
407 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
Dgfx_v8_0.c207 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
320 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
351 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
383 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
424 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
482 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
579 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
684 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
Dgfx_v9_0.c521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
Dgfx_v10_0.c212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
Dgfx_v7_0.c1991 WREG32(mmTA_CNTL_AUX, 0x00010000); in gfx_v7_0_constants_init()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1573 #define mmTA_CNTL_AUX 0x2542 macro
Dgfx_7_2_d.h2105 #define mmTA_CNTL_AUX 0x2542 macro
Dgfx_7_0_d.h2084 #define mmTA_CNTL_AUX 0x2542 macro
Dgfx_8_1_d.h2276 #define mmTA_CNTL_AUX 0x2542 macro
Dgfx_8_0_d.h2297 #define mmTA_CNTL_AUX 0x2542 macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h847 #define mmTA_CNTL_AUX macro
Dgc_9_2_1_offset.h795 #define mmTA_CNTL_AUX macro
Dgc_9_1_offset.h819 #define mmTA_CNTL_AUX macro
Dgc_10_1_0_offset.h2747 #define mmTA_CNTL_AUX macro