Home
last modified time | relevance | path

Searched refs:mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h658 #define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX … macro
Dgc_9_1_offset.h652 #define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX … macro
Dgc_9_2_1_offset.h630 #define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX … macro