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Searched refs:mmRLC_SRM_INDEX_CNTL_ADDR_0 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c712 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
713 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
714 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
715 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
716 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
717 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
718 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
719 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
2783 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) in gfx_v9_1_init_rlc_save_restore_list()
Dgfx_v8_0.c4010 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; in gfx_v8_0_init_save_restore_list()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_d.h1463 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
Dgfx_8_1_d.h1459 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6159 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 macro
Dgc_9_1_offset.h6381 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 macro
Dgc_9_2_1_offset.h6357 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 macro
Dgc_10_1_0_offset.h9465 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 macro
Dgc_10_3_0_offset.h9291 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 macro