Searched refs:mmRLC_MEM_SLP_CNTL (Results 1 – 14 of 14) sorted by relevance
| /Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 1156 #define mmRLC_MEM_SLP_CNTL 0x30D8 macro
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| D | gfx_7_0_d.h | 1247 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
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| D | gfx_7_2_d.h | 1260 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
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| D | gfx_8_0_d.h | 1349 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
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| D | gfx_8_1_d.h | 1351 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
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| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 4802 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4805 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4831 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4834 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5132 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
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| D | gfx_v8_0.c | 708 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5499 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5714 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5717 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
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| D | gfx_v10_0.c | 7364 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7367 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7395 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7398 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7669 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
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| D | gfx_v7_0.c | 3678 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3681 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
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| /Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 5969 #define mmRLC_MEM_SLP_CNTL … macro
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| D | gc_9_1_offset.h | 6191 #define mmRLC_MEM_SLP_CNTL … macro
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| D | gc_9_2_1_offset.h | 6155 #define mmRLC_MEM_SLP_CNTL … macro
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| D | gc_10_1_0_offset.h | 9279 #define mmRLC_MEM_SLP_CNTL … macro
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| D | gc_10_3_0_offset.h | 9075 #define mmRLC_MEM_SLP_CNTL … macro
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