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Searched refs:mmMP1_SMN_IH_SW_INT_CTRL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_10_0_offset.h330 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_12_0_0_offset.h330 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_11_0_offset.h334 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_9_0_offset.h344 #define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 macro
/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsmu_v11_0.c1234 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); in smu_v11_0_set_irq_state()
1236 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); in smu_v11_0_set_irq_state()
1267 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); in smu_v11_0_set_irq_state()
1269 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); in smu_v11_0_set_irq_state()
1327 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); in smu_v11_0_irq_process()
1329 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); in smu_v11_0_irq_process()