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Searched refs:mmMP0_SMN_C2PMSG_67 (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dpsp_v10_0.c228 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v10_0_ring_get_wptr()
235 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v10_0_ring_set_wptr()
Dpsp_v3_1.c384 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v3_1_ring_get_wptr()
398 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v3_1_ring_set_wptr()
Dpsp_v12_0.c403 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v12_0_ring_get_wptr()
416 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v12_0_ring_set_wptr()
Dpsp_v11_0.c737 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v11_0_ring_get_wptr()
750 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v11_0_ring_set_wptr()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_10_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 … macro
Dmp_12_0_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 … macro
Dmp_11_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 … macro
Dmp_9_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 0x0083 macro