1  /* SPDX-License-Identifier: GPL-2.0
2   *
3   * Copyright 2016-2018 HabanaLabs, Ltd.
4   * All Rights Reserved.
5   *
6   */
7  
8  /************************************
9   ** This is an auto-generated file **
10   **       DO NOT EDIT BELOW        **
11   ************************************/
12  
13  #ifndef ASIC_REG_MME1_RTR_REGS_H_
14  #define ASIC_REG_MME1_RTR_REGS_H_
15  
16  /*
17   *****************************************
18   *   MME1_RTR (Prototype: MME_RTR)
19   *****************************************
20   */
21  
22  #define mmMME1_RTR_HBW_RD_RQ_E_ARB                                   0x40100
23  
24  #define mmMME1_RTR_HBW_RD_RQ_W_ARB                                   0x40104
25  
26  #define mmMME1_RTR_HBW_RD_RQ_N_ARB                                   0x40108
27  
28  #define mmMME1_RTR_HBW_RD_RQ_S_ARB                                   0x4010C
29  
30  #define mmMME1_RTR_HBW_RD_RQ_L_ARB                                   0x40110
31  
32  #define mmMME1_RTR_HBW_E_ARB_MAX                                     0x40120
33  
34  #define mmMME1_RTR_HBW_W_ARB_MAX                                     0x40124
35  
36  #define mmMME1_RTR_HBW_N_ARB_MAX                                     0x40128
37  
38  #define mmMME1_RTR_HBW_S_ARB_MAX                                     0x4012C
39  
40  #define mmMME1_RTR_HBW_L_ARB_MAX                                     0x40130
41  
42  #define mmMME1_RTR_HBW_RD_RS_MAX_CREDIT                              0x40140
43  
44  #define mmMME1_RTR_HBW_WR_RQ_MAX_CREDIT                              0x40144
45  
46  #define mmMME1_RTR_HBW_RD_RQ_MAX_CREDIT                              0x40148
47  
48  #define mmMME1_RTR_HBW_RD_RS_E_ARB                                   0x40150
49  
50  #define mmMME1_RTR_HBW_RD_RS_W_ARB                                   0x40154
51  
52  #define mmMME1_RTR_HBW_RD_RS_N_ARB                                   0x40158
53  
54  #define mmMME1_RTR_HBW_RD_RS_S_ARB                                   0x4015C
55  
56  #define mmMME1_RTR_HBW_RD_RS_L_ARB                                   0x40160
57  
58  #define mmMME1_RTR_HBW_WR_RQ_E_ARB                                   0x40170
59  
60  #define mmMME1_RTR_HBW_WR_RQ_W_ARB                                   0x40174
61  
62  #define mmMME1_RTR_HBW_WR_RQ_N_ARB                                   0x40178
63  
64  #define mmMME1_RTR_HBW_WR_RQ_S_ARB                                   0x4017C
65  
66  #define mmMME1_RTR_HBW_WR_RQ_L_ARB                                   0x40180
67  
68  #define mmMME1_RTR_HBW_WR_RS_E_ARB                                   0x40190
69  
70  #define mmMME1_RTR_HBW_WR_RS_W_ARB                                   0x40194
71  
72  #define mmMME1_RTR_HBW_WR_RS_N_ARB                                   0x40198
73  
74  #define mmMME1_RTR_HBW_WR_RS_S_ARB                                   0x4019C
75  
76  #define mmMME1_RTR_HBW_WR_RS_L_ARB                                   0x401A0
77  
78  #define mmMME1_RTR_LBW_RD_RQ_E_ARB                                   0x40200
79  
80  #define mmMME1_RTR_LBW_RD_RQ_W_ARB                                   0x40204
81  
82  #define mmMME1_RTR_LBW_RD_RQ_N_ARB                                   0x40208
83  
84  #define mmMME1_RTR_LBW_RD_RQ_S_ARB                                   0x4020C
85  
86  #define mmMME1_RTR_LBW_RD_RQ_L_ARB                                   0x40210
87  
88  #define mmMME1_RTR_LBW_E_ARB_MAX                                     0x40220
89  
90  #define mmMME1_RTR_LBW_W_ARB_MAX                                     0x40224
91  
92  #define mmMME1_RTR_LBW_N_ARB_MAX                                     0x40228
93  
94  #define mmMME1_RTR_LBW_S_ARB_MAX                                     0x4022C
95  
96  #define mmMME1_RTR_LBW_L_ARB_MAX                                     0x40230
97  
98  #define mmMME1_RTR_LBW_SRAM_MAX_CREDIT                               0x40240
99  
100  #define mmMME1_RTR_LBW_RD_RS_E_ARB                                   0x40250
101  
102  #define mmMME1_RTR_LBW_RD_RS_W_ARB                                   0x40254
103  
104  #define mmMME1_RTR_LBW_RD_RS_N_ARB                                   0x40258
105  
106  #define mmMME1_RTR_LBW_RD_RS_S_ARB                                   0x4025C
107  
108  #define mmMME1_RTR_LBW_RD_RS_L_ARB                                   0x40260
109  
110  #define mmMME1_RTR_LBW_WR_RQ_E_ARB                                   0x40270
111  
112  #define mmMME1_RTR_LBW_WR_RQ_W_ARB                                   0x40274
113  
114  #define mmMME1_RTR_LBW_WR_RQ_N_ARB                                   0x40278
115  
116  #define mmMME1_RTR_LBW_WR_RQ_S_ARB                                   0x4027C
117  
118  #define mmMME1_RTR_LBW_WR_RQ_L_ARB                                   0x40280
119  
120  #define mmMME1_RTR_LBW_WR_RS_E_ARB                                   0x40290
121  
122  #define mmMME1_RTR_LBW_WR_RS_W_ARB                                   0x40294
123  
124  #define mmMME1_RTR_LBW_WR_RS_N_ARB                                   0x40298
125  
126  #define mmMME1_RTR_LBW_WR_RS_S_ARB                                   0x4029C
127  
128  #define mmMME1_RTR_LBW_WR_RS_L_ARB                                   0x402A0
129  
130  #define mmMME1_RTR_DBG_E_ARB                                         0x40300
131  
132  #define mmMME1_RTR_DBG_W_ARB                                         0x40304
133  
134  #define mmMME1_RTR_DBG_N_ARB                                         0x40308
135  
136  #define mmMME1_RTR_DBG_S_ARB                                         0x4030C
137  
138  #define mmMME1_RTR_DBG_L_ARB                                         0x40310
139  
140  #define mmMME1_RTR_DBG_E_ARB_MAX                                     0x40320
141  
142  #define mmMME1_RTR_DBG_W_ARB_MAX                                     0x40324
143  
144  #define mmMME1_RTR_DBG_N_ARB_MAX                                     0x40328
145  
146  #define mmMME1_RTR_DBG_S_ARB_MAX                                     0x4032C
147  
148  #define mmMME1_RTR_DBG_L_ARB_MAX                                     0x40330
149  
150  #define mmMME1_RTR_SPLIT_COEF_0                                      0x40400
151  
152  #define mmMME1_RTR_SPLIT_COEF_1                                      0x40404
153  
154  #define mmMME1_RTR_SPLIT_COEF_2                                      0x40408
155  
156  #define mmMME1_RTR_SPLIT_COEF_3                                      0x4040C
157  
158  #define mmMME1_RTR_SPLIT_COEF_4                                      0x40410
159  
160  #define mmMME1_RTR_SPLIT_COEF_5                                      0x40414
161  
162  #define mmMME1_RTR_SPLIT_COEF_6                                      0x40418
163  
164  #define mmMME1_RTR_SPLIT_COEF_7                                      0x4041C
165  
166  #define mmMME1_RTR_SPLIT_COEF_8                                      0x40420
167  
168  #define mmMME1_RTR_SPLIT_COEF_9                                      0x40424
169  
170  #define mmMME1_RTR_SPLIT_CFG                                         0x40440
171  
172  #define mmMME1_RTR_SPLIT_RD_SAT                                      0x40444
173  
174  #define mmMME1_RTR_SPLIT_RD_RST_TOKEN                                0x40448
175  
176  #define mmMME1_RTR_SPLIT_RD_TIMEOUT_0                                0x4044C
177  
178  #define mmMME1_RTR_SPLIT_RD_TIMEOUT_1                                0x40450
179  
180  #define mmMME1_RTR_SPLIT_WR_SAT                                      0x40454
181  
182  #define mmMME1_RTR_WPLIT_WR_TST_TOLEN                                0x40458
183  
184  #define mmMME1_RTR_SPLIT_WR_TIMEOUT_0                                0x4045C
185  
186  #define mmMME1_RTR_SPLIT_WR_TIMEOUT_1                                0x40460
187  
188  #define mmMME1_RTR_HBW_RANGE_HIT                                     0x40470
189  
190  #define mmMME1_RTR_HBW_RANGE_MASK_L_0                                0x40480
191  
192  #define mmMME1_RTR_HBW_RANGE_MASK_L_1                                0x40484
193  
194  #define mmMME1_RTR_HBW_RANGE_MASK_L_2                                0x40488
195  
196  #define mmMME1_RTR_HBW_RANGE_MASK_L_3                                0x4048C
197  
198  #define mmMME1_RTR_HBW_RANGE_MASK_L_4                                0x40490
199  
200  #define mmMME1_RTR_HBW_RANGE_MASK_L_5                                0x40494
201  
202  #define mmMME1_RTR_HBW_RANGE_MASK_L_6                                0x40498
203  
204  #define mmMME1_RTR_HBW_RANGE_MASK_L_7                                0x4049C
205  
206  #define mmMME1_RTR_HBW_RANGE_MASK_H_0                                0x404A0
207  
208  #define mmMME1_RTR_HBW_RANGE_MASK_H_1                                0x404A4
209  
210  #define mmMME1_RTR_HBW_RANGE_MASK_H_2                                0x404A8
211  
212  #define mmMME1_RTR_HBW_RANGE_MASK_H_3                                0x404AC
213  
214  #define mmMME1_RTR_HBW_RANGE_MASK_H_4                                0x404B0
215  
216  #define mmMME1_RTR_HBW_RANGE_MASK_H_5                                0x404B4
217  
218  #define mmMME1_RTR_HBW_RANGE_MASK_H_6                                0x404B8
219  
220  #define mmMME1_RTR_HBW_RANGE_MASK_H_7                                0x404BC
221  
222  #define mmMME1_RTR_HBW_RANGE_BASE_L_0                                0x404C0
223  
224  #define mmMME1_RTR_HBW_RANGE_BASE_L_1                                0x404C4
225  
226  #define mmMME1_RTR_HBW_RANGE_BASE_L_2                                0x404C8
227  
228  #define mmMME1_RTR_HBW_RANGE_BASE_L_3                                0x404CC
229  
230  #define mmMME1_RTR_HBW_RANGE_BASE_L_4                                0x404D0
231  
232  #define mmMME1_RTR_HBW_RANGE_BASE_L_5                                0x404D4
233  
234  #define mmMME1_RTR_HBW_RANGE_BASE_L_6                                0x404D8
235  
236  #define mmMME1_RTR_HBW_RANGE_BASE_L_7                                0x404DC
237  
238  #define mmMME1_RTR_HBW_RANGE_BASE_H_0                                0x404E0
239  
240  #define mmMME1_RTR_HBW_RANGE_BASE_H_1                                0x404E4
241  
242  #define mmMME1_RTR_HBW_RANGE_BASE_H_2                                0x404E8
243  
244  #define mmMME1_RTR_HBW_RANGE_BASE_H_3                                0x404EC
245  
246  #define mmMME1_RTR_HBW_RANGE_BASE_H_4                                0x404F0
247  
248  #define mmMME1_RTR_HBW_RANGE_BASE_H_5                                0x404F4
249  
250  #define mmMME1_RTR_HBW_RANGE_BASE_H_6                                0x404F8
251  
252  #define mmMME1_RTR_HBW_RANGE_BASE_H_7                                0x404FC
253  
254  #define mmMME1_RTR_LBW_RANGE_HIT                                     0x40500
255  
256  #define mmMME1_RTR_LBW_RANGE_MASK_0                                  0x40510
257  
258  #define mmMME1_RTR_LBW_RANGE_MASK_1                                  0x40514
259  
260  #define mmMME1_RTR_LBW_RANGE_MASK_2                                  0x40518
261  
262  #define mmMME1_RTR_LBW_RANGE_MASK_3                                  0x4051C
263  
264  #define mmMME1_RTR_LBW_RANGE_MASK_4                                  0x40520
265  
266  #define mmMME1_RTR_LBW_RANGE_MASK_5                                  0x40524
267  
268  #define mmMME1_RTR_LBW_RANGE_MASK_6                                  0x40528
269  
270  #define mmMME1_RTR_LBW_RANGE_MASK_7                                  0x4052C
271  
272  #define mmMME1_RTR_LBW_RANGE_MASK_8                                  0x40530
273  
274  #define mmMME1_RTR_LBW_RANGE_MASK_9                                  0x40534
275  
276  #define mmMME1_RTR_LBW_RANGE_MASK_10                                 0x40538
277  
278  #define mmMME1_RTR_LBW_RANGE_MASK_11                                 0x4053C
279  
280  #define mmMME1_RTR_LBW_RANGE_MASK_12                                 0x40540
281  
282  #define mmMME1_RTR_LBW_RANGE_MASK_13                                 0x40544
283  
284  #define mmMME1_RTR_LBW_RANGE_MASK_14                                 0x40548
285  
286  #define mmMME1_RTR_LBW_RANGE_MASK_15                                 0x4054C
287  
288  #define mmMME1_RTR_LBW_RANGE_BASE_0                                  0x40550
289  
290  #define mmMME1_RTR_LBW_RANGE_BASE_1                                  0x40554
291  
292  #define mmMME1_RTR_LBW_RANGE_BASE_2                                  0x40558
293  
294  #define mmMME1_RTR_LBW_RANGE_BASE_3                                  0x4055C
295  
296  #define mmMME1_RTR_LBW_RANGE_BASE_4                                  0x40560
297  
298  #define mmMME1_RTR_LBW_RANGE_BASE_5                                  0x40564
299  
300  #define mmMME1_RTR_LBW_RANGE_BASE_6                                  0x40568
301  
302  #define mmMME1_RTR_LBW_RANGE_BASE_7                                  0x4056C
303  
304  #define mmMME1_RTR_LBW_RANGE_BASE_8                                  0x40570
305  
306  #define mmMME1_RTR_LBW_RANGE_BASE_9                                  0x40574
307  
308  #define mmMME1_RTR_LBW_RANGE_BASE_10                                 0x40578
309  
310  #define mmMME1_RTR_LBW_RANGE_BASE_11                                 0x4057C
311  
312  #define mmMME1_RTR_LBW_RANGE_BASE_12                                 0x40580
313  
314  #define mmMME1_RTR_LBW_RANGE_BASE_13                                 0x40584
315  
316  #define mmMME1_RTR_LBW_RANGE_BASE_14                                 0x40588
317  
318  #define mmMME1_RTR_LBW_RANGE_BASE_15                                 0x4058C
319  
320  #define mmMME1_RTR_RGLTR                                             0x40590
321  
322  #define mmMME1_RTR_RGLTR_WR_RESULT                                   0x40594
323  
324  #define mmMME1_RTR_RGLTR_RD_RESULT                                   0x40598
325  
326  #define mmMME1_RTR_SCRAMB_EN                                         0x40600
327  
328  #define mmMME1_RTR_NON_LIN_SCRAMB                                    0x40604
329  
330  #endif /* ASIC_REG_MME1_RTR_REGS_H_ */
331