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Searched refs:mmMC_SEQ_SUP_CNTL (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c174 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
179 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
180 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
193 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v6_0_mc_load_microcode()
195 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v6_0_mc_load_microcode()
Dgmc_v8_0.c328 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
333 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
345 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
346 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
347 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
407 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
408 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
415 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
416 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
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Dgmc_v7_0.c203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v7_0_mc_load_microcode()
222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v7_0_mc_load_microcode()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h949 #define mmMC_SEQ_SUP_CNTL 0x0A32 macro
Dgmc_7_1_d.h784 #define mmMC_SEQ_SUP_CNTL 0xa32 macro
Dgmc_8_1_d.h888 #define mmMC_SEQ_SUP_CNTL 0xa32 macro