1  /* SPDX-License-Identifier: GPL-2.0
2   *
3   * Copyright 2016-2018 HabanaLabs, Ltd.
4   * All Rights Reserved.
5   *
6   */
7  
8  /************************************
9   ** This is an auto-generated file **
10   **       DO NOT EDIT BELOW        **
11   ************************************/
12  
13  #ifndef ASIC_REG_MC_PLL_REGS_H_
14  #define ASIC_REG_MC_PLL_REGS_H_
15  
16  /*
17   *****************************************
18   *   MC_PLL (Prototype: PLL)
19   *****************************************
20   */
21  
22  #define mmMC_PLL_NR                                                  0x4A1100
23  
24  #define mmMC_PLL_NF                                                  0x4A1104
25  
26  #define mmMC_PLL_OD                                                  0x4A1108
27  
28  #define mmMC_PLL_NB                                                  0x4A110C
29  
30  #define mmMC_PLL_CFG                                                 0x4A1110
31  
32  #define mmMC_PLL_LOSE_MASK                                           0x4A1120
33  
34  #define mmMC_PLL_LOCK_INTR                                           0x4A1128
35  
36  #define mmMC_PLL_LOCK_BYPASS                                         0x4A112C
37  
38  #define mmMC_PLL_DATA_CHNG                                           0x4A1130
39  
40  #define mmMC_PLL_RST                                                 0x4A1134
41  
42  #define mmMC_PLL_SLIP_WD_CNTR                                        0x4A1150
43  
44  #define mmMC_PLL_DIV_FACTOR_0                                        0x4A1200
45  
46  #define mmMC_PLL_DIV_FACTOR_1                                        0x4A1204
47  
48  #define mmMC_PLL_DIV_FACTOR_2                                        0x4A1208
49  
50  #define mmMC_PLL_DIV_FACTOR_3                                        0x4A120C
51  
52  #define mmMC_PLL_DIV_FACTOR_CMD_0                                    0x4A1220
53  
54  #define mmMC_PLL_DIV_FACTOR_CMD_1                                    0x4A1224
55  
56  #define mmMC_PLL_DIV_FACTOR_CMD_2                                    0x4A1228
57  
58  #define mmMC_PLL_DIV_FACTOR_CMD_3                                    0x4A122C
59  
60  #define mmMC_PLL_DIV_SEL_0                                           0x4A1280
61  
62  #define mmMC_PLL_DIV_SEL_1                                           0x4A1284
63  
64  #define mmMC_PLL_DIV_SEL_2                                           0x4A1288
65  
66  #define mmMC_PLL_DIV_SEL_3                                           0x4A128C
67  
68  #define mmMC_PLL_DIV_EN_0                                            0x4A12A0
69  
70  #define mmMC_PLL_DIV_EN_1                                            0x4A12A4
71  
72  #define mmMC_PLL_DIV_EN_2                                            0x4A12A8
73  
74  #define mmMC_PLL_DIV_EN_3                                            0x4A12AC
75  
76  #define mmMC_PLL_DIV_FACTOR_BUSY_0                                   0x4A12C0
77  
78  #define mmMC_PLL_DIV_FACTOR_BUSY_1                                   0x4A12C4
79  
80  #define mmMC_PLL_DIV_FACTOR_BUSY_2                                   0x4A12C8
81  
82  #define mmMC_PLL_DIV_FACTOR_BUSY_3                                   0x4A12CC
83  
84  #define mmMC_PLL_CLK_GATER                                           0x4A1300
85  
86  #define mmMC_PLL_CLK_RLX_0                                           0x4A1310
87  
88  #define mmMC_PLL_CLK_RLX_1                                           0x4A1314
89  
90  #define mmMC_PLL_CLK_RLX_2                                           0x4A1318
91  
92  #define mmMC_PLL_CLK_RLX_3                                           0x4A131C
93  
94  #define mmMC_PLL_REF_CNTR_PERIOD                                     0x4A1400
95  
96  #define mmMC_PLL_REF_LOW_THRESHOLD                                   0x4A1410
97  
98  #define mmMC_PLL_REF_HIGH_THRESHOLD                                  0x4A1420
99  
100  #define mmMC_PLL_PLL_NOT_STABLE                                      0x4A1430
101  
102  #define mmMC_PLL_FREQ_CALC_EN                                        0x4A1440
103  
104  #endif /* ASIC_REG_MC_PLL_REGS_H_ */
105