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Searched refs:mmLVTMA_PWRSEQ_CNTL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h11352 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h10394 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h12769 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h12579 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1851 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … macro