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Searched refs:mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_2_1_offset.h1694 #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro
Dgc_9_1_offset.h1752 #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro
Dgc_10_1_0_offset.h3774 #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro
Dgc_10_3_0_offset.h3719 #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … macro