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Searched refs:mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_0_offset.h15537 #define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
Ddcn_3_0_0_offset.h7389 #define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro