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Searched refs:mmDP5_DP_VID_TIMING_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h9914 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
Ddcn_2_0_0_offset.h12601 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
Ddcn_3_0_0_offset.h12399 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h11631 #define mmDP5_DP_VID_TIMING_BASE_IDX … macro