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Searched refs:mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h10008 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro
Ddcn_2_0_0_offset.h12695 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro
Ddcn_3_0_0_offset.h12493 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … macro