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Searched refs:mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h663 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … macro
Ddcn_2_1_0_offset.h301 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … macro
Ddcn_2_0_0_offset.h311 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_0_0_offset.h292 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … macro