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Searched refs:mmCP_MEC1_F32_INT_DIS (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_d.h285 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
Dgfx_8_1_d.h286 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2611 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_9_1_offset.h2881 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_9_2_1_offset.h2815 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_10_1_0_offset.h4941 #define mmCP_MEC1_F32_INT_DIS macro
Dgc_10_3_0_offset.h4592 #define mmCP_MEC1_F32_INT_DIS macro