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Searched refs:mmCP_HQD_PQ_DOORBELL_CONTROL (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c621 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in mes_v10_1_mqd_init()
689 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in mes_v10_1_mqd_init()
739 data = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in mes_v10_1_queue_init_register()
742 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v10_1_queue_init_register()
773 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in mes_v10_1_queue_init_register()
Damdgpu_amdkfd_gfx_v7.c236 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
430 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); in kgd_hqd_destroy()
Damdgpu_amdkfd_gfx_v8.c223 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
Damdgpu_amdkfd_gfx_v10.c249 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_hqd_load()
Damdgpu_amdkfd_gfx_v9.c260 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_gfx_v9_hqd_load()
Damdgpu_amdkfd_gfx_v10_3.c234 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v10_3()
Dgfx_v9_0.c3432 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_0_mqd_init()
3500 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_0_mqd_init()
3562 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_0_kiq_init_register()
3623 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_0_kiq_init_register()
3678 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_0_kiq_fini_register()
3679 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_0_kiq_fini_register()
Dgfx_v7_0.c2939 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2994 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
Dgfx_v10_0.c6398 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v10_0_compute_mqd_init()
6466 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v10_0_compute_mqd_init()
6532 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v10_0_kiq_init_register()
6593 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v10_0_kiq_init_register()
Dgfx_v8_0.c4474 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL), in gfx_v8_0_mqd_init()
4524 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v8_0_mqd_init()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h582 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
Dgfx_7_2_d.h595 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
Dgfx_8_0_d.h645 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
Dgfx_8_1_d.h645 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2849 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_9_1_offset.h3077 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_9_2_1_offset.h3033 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_10_1_0_offset.h5313 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_10_3_0_offset.h4946 #define mmCP_HQD_PQ_DOORBELL_CONTROL … macro