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Searched refs:mmCP_CPC_IC_OP_CNTL (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_d.h349 #define mmCP_CPC_IC_OP_CNTL 0x30bc macro
Dgfx_8_1_d.h349 #define mmCP_CPC_IC_OP_CNTL 0x30bc macro
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c5393 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5395 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5399 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
6043 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_cp_compute_load_microcode()
6045 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
6049 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); in gfx_v10_0_cp_compute_load_microcode()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2609 #define mmCP_CPC_IC_OP_CNTL macro
Dgc_9_1_offset.h2879 #define mmCP_CPC_IC_OP_CNTL macro
Dgc_9_2_1_offset.h2813 #define mmCP_CPC_IC_OP_CNTL macro
Dgc_10_1_0_offset.h10265 #define mmCP_CPC_IC_OP_CNTL macro
Dgc_10_3_0_offset.h9875 #define mmCP_CPC_IC_OP_CNTL macro