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Searched refs:min_clocks (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c1558 struct smu_clocks min_clocks = {0}; in navi10_notify_smc_display_config() local
1562 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_display_config()
1563 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_display_config()
1564 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
1568 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_display_config()
1575 min_clocks.dcef_clock_in_sr/100, in navi10_notify_smc_display_config()
1588 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
Dsienna_cichlid_ppt.c1374 struct smu_clocks min_clocks = {0}; in sienna_cichlid_notify_smc_display_config() local
1378 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in sienna_cichlid_notify_smc_display_config()
1379 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in sienna_cichlid_notify_smc_display_config()
1380 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1384 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in sienna_cichlid_notify_smc_display_config()
1391 min_clocks.dcef_clock_in_sr/100, in sienna_cichlid_notify_smc_display_config()
1404 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c1500 struct PP_Clocks min_clocks = {0}; in vega12_notify_smc_display_config_after_ps_adjustment() local
1510 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1511 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1512 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1516 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; in vega12_notify_smc_display_config_after_ps_adjustment()
1522 min_clocks.dcefClockInSR /100, in vega12_notify_smc_display_config_after_ps_adjustment()
Dvega20_hwmgr.c2306 struct PP_Clocks min_clocks = {0}; in vega20_notify_smc_display_config_after_ps_adjustment() local
2310 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2311 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2312 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
2316 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()
2321 min_clocks.dcefClockInSR / 100, in vega20_notify_smc_display_config_after_ps_adjustment()
2331 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; in vega20_notify_smc_display_config_after_ps_adjustment()
Dvega10_hwmgr.c3977 struct PP_Clocks min_clocks = {0}; in vega10_notify_smc_display_config_after_ps_adjustment() local
3988 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
3989 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
3990 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
3993 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) in vega10_notify_smc_display_config_after_ps_adjustment()
4003 min_clocks.dcefClockInSR / 100, in vega10_notify_smc_display_config_after_ps_adjustment()
4012 if (min_clocks.memoryClock != 0) { in vega10_notify_smc_display_config_after_ps_adjustment()
4013 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); in vega10_notify_smc_display_config_after_ps_adjustment()
Dsmu7_hwmgr.c3632 struct PP_Clocks min_clocks = {0}; in smu7_find_dpm_states_clocks_in_dpm_table() local
3649 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && in smu7_find_dpm_states_clocks_in_dpm_table()
3650 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || in smu7_find_dpm_states_clocks_in_dpm_table()