Searched refs:mg_pll_div1 (Results 1 – 4 of 4) sorted by relevance
205 u32 mg_pll_div1; member
3294 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()3315 pll_state->mg_pll_div1 = in icl_calc_mg_pll_state()3401 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()3703 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()3779 hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()3780 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()3929 intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()3992 val |= hw_state->mg_pll_div1; in dkl_pll_write()4212 hw_state->mg_pll_div1, in icl_dump_hw_state()
953 pll->state.hw_state.mg_pll_div1); in i915_shared_dplls_info()
14014 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); in intel_pipe_config_compare()
