Searched refs:max_handles (Results 1 – 13 of 13) sorted by relevance
62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()166 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()186 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()219 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_init()256 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_suspend()331 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_free_handles()516 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()542 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()557 for (i = 0; i < p->rdev->uvd.max_handles; ++i) in radeon_uvd_cs_msg()859 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_count_handles()
125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
1678 unsigned max_handles; member
233 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; in amdgpu_uvd_sw_init()254 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()273 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()279 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; in amdgpu_uvd_sw_init()295 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_sw_init()385 for (i = 0; i < adev->uvd.max_handles; ++i) in amdgpu_uvd_suspend()389 if (i == adev->uvd.max_handles) in amdgpu_uvd_suspend()463 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_free_handles()785 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()809 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()[all …]
57 unsigned max_handles; member
557 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
254 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v3_1_mc_resume()
274 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
604 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v6_0_mc_resume()612 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v6_0_mc_resume()
703 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v7_0_mc_resume()839 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); in uvd_v7_0_sriov_start()
852 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()
