Searched refs:level1 (Results 1 – 8 of 8) sorted by relevance
94 u32 level1; member106 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_suspend()118 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_resume()
749 u32 level1; in mtu3_irq() local754 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR); in mtu3_irq()755 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER); in mtu3_irq()757 if (level1 & EP_CTRL_INTR) in mtu3_irq()760 if (level1 & MAC2_INTR) in mtu3_irq()763 if (level1 & MAC3_INTR) in mtu3_irq()766 if (level1 & BMU_INTR) in mtu3_irq()769 if (level1 & QMU_INTR) in mtu3_irq()
71 struct i40iw_pble_info level1; member
516 struct i40iw_pble_info *lvl1 = &palloc->level1; in get_lvl1_pble()609 gen_pool_free(pool, palloc->level1.addr, in i40iw_free_pble()610 (palloc->level1.cnt << 3)); in i40iw_free_pble()
1351 arr = (u64 *)palloc->level1.addr; in i40iw_check_mr_contiguous()1396 pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf; in i40iw_setup_pbles()1447 arr = (u64 *)palloc->level1.addr; in i40iw_handle_q_mem()1460 hmc_p->idx = palloc->level1.idx; in i40iw_handle_q_mem()1462 hmc_p->idx = palloc->level1.idx + req->sq_pages; in i40iw_handle_q_mem()1476 hmc_p->idx = palloc->level1.idx; in i40iw_handle_q_mem()1604 pbl = (u64 *)palloc->level1.addr; in i40iw_set_page()1687 stag_info->first_pm_pbl_index = palloc->level1.idx; in i40iw_hwreg_mr()2229 info.reg_addr_pa = *(u64 *)palloc->level1.addr; in i40iw_post_send()2230 info.first_pm_pbl_index = palloc->level1.idx; in i40iw_post_send()
319 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0343 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
92 ldr r12, omap_ih1_base @ set pointer to level1 handler
3454 int level1 = 0, level2 = 0; in ilk_find_best_result() local3458 level1 = level; in ilk_find_best_result()3463 if (level1 == level2) { in ilk_find_best_result()3468 } else if (level1 > level2) { in ilk_find_best_result()
