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Searched refs:lane (Results 1 – 25 of 169) sorted by relevance

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/Linux-v5.10/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c180 unsigned lane; member
188 .lane = _lane, \
198 .lane = _lane, \
272 unsigned long lane, unsigned long mode) in mvebu_comphy_smc() argument
277 arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); in mvebu_comphy_smc()
290 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, in mvebu_comphy_get_mode() argument
304 if (conf->lane == lane && in mvebu_comphy_get_mode()
320 static inline int mvebu_comphy_get_mux(int lane, int port, in mvebu_comphy_get_mux() argument
323 return mvebu_comphy_get_mode(false, lane, port, mode, submode); in mvebu_comphy_get_mux()
326 static inline int mvebu_comphy_get_fw_mode(int lane, int port, in mvebu_comphy_get_fw_mode() argument
[all …]
Dphy-mvebu-a3700-comphy.c58 unsigned int lane; member
67 .lane = _lane, \
110 static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, in mvebu_a3700_comphy_smc() argument
116 arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); in mvebu_a3700_comphy_smc()
129 static int mvebu_a3700_comphy_get_fw_mode(int lane, int port, in mvebu_a3700_comphy_get_fw_mode() argument
140 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_get_fw_mode()
156 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_set_mode() local
162 fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode, in mvebu_a3700_comphy_set_mode()
165 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_set_mode()
170 lane->mode = mode; in mvebu_a3700_comphy_set_mode()
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Dphy-armada38x-comphy.c46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
78 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
79 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
82 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
85 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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/Linux-v5.10/drivers/net/dsa/b53/
Db53_serdes.c37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
39 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
42 WARN_ON(lane > 1); in b53_serdes_set_lane()
45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
46 dev->serdes_lane = lane; in b53_serdes_set_lane()
49 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
52 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
59 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
66 u8 lane = b53_serdes_map_lane(dev, port); in b53_serdes_config() local
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/Linux-v5.10/drivers/net/dsa/mv88e6xxx/
Dserdes.c37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
98 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, in mv88e6352_serdes_power() argument
120 u8 lane, unsigned int mode, in mv88e6352_serdes_pcs_config() argument
169 u8 lane, struct phylink_link_state *state) in mv88e6352_serdes_pcs_get_state() argument
190 u8 lane) in mv88e6352_serdes_pcs_an_restart() argument
203 u8 lane, int speed, int duplex) in mv88e6352_serdes_pcs_link_up() argument
236 u8 lane = 0; in mv88e6352_serdes_get_lane() local
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Dserdes.h81 u8 lane, unsigned int mode,
85 u8 lane, unsigned int mode,
89 u8 lane, struct phylink_link_state *state);
91 u8 lane, struct phylink_link_state *state);
93 u8 lane);
95 u8 lane);
97 u8 lane, int speed, int duplex);
99 u8 lane, int speed, int duplex);
104 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
106 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
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/Linux-v5.10/drivers/phy/
Dphy-xgene.c657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
698 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
700 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
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/Linux-v5.10/drivers/phy/tegra/
Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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Dxusb.c109 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
112 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
120 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
127 lane->function = err; in tegra_xusb_lane_parse_dt()
135 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
137 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
185 struct phy *lane; in tegra_xusb_pad_register() local
193 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
202 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
217 lane = pad->ops->probe(pad, np, i); in tegra_xusb_pad_register()
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Dxusb-tegra210.c822 struct tegra_xusb_lane *lane; in tegra210_usb3_set_lfps_detect() local
829 lane = port->lane; in tegra210_usb3_set_lfps_detect()
831 if (lane->pad == padctl->pcie) in tegra210_usb3_set_lfps_detect()
832 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); in tegra210_usb3_set_lfps_detect()
904 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra210_usb2_lane_remove() argument
906 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra210_usb2_lane_remove()
918 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_usb2_phy_init() local
919 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_init()
934 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra210_usb2_phy_exit() local
936 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_usb2_phy_exit()
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Dxusb.h49 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
57 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
59 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
70 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
72 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
80 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
82 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
99 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
101 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
109 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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Dxusb-tegra186.c176 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
178 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
256 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_phy_xusb_utmi_pad_power_on() local
257 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra_phy_xusb_utmi_pad_power_on()
260 unsigned int index = lane->index; in tegra_phy_xusb_utmi_pad_power_on()
287 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_phy_xusb_utmi_pad_power_down() local
288 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra_phy_xusb_utmi_pad_power_down()
289 unsigned int index = lane->index; in tegra_phy_xusb_utmi_pad_power_down()
363 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra186_utmi_phy_set_mode() local
364 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_phy_set_mode()
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/Linux-v5.10/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c238 int pre_emphasis, int lane) in analogix_dp_set_lane_lane_pre_emphasis() argument
240 switch (lane) { in analogix_dp_set_lane_lane_pre_emphasis()
261 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
269 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
289 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
291 PRE_EMPHASIS_LEVEL_0, lane); in analogix_dp_link_start()
315 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
316 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in analogix_dp_link_start()
327 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
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/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c58 int lane; in intel_dp_get_adjust_train() local
62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
63 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); in intel_dp_get_adjust_train()
64 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); in intel_dp_get_adjust_train()
85 for (lane = 0; lane < 4; lane++) in intel_dp_get_adjust_train()
86 intel_dp->train_set[lane] = v | p; in intel_dp_get_adjust_train()
139 int lane; in intel_dp_link_max_vswing_reached() local
141 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
142 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c289 uint32_t lane; in dpcd_set_lt_pattern_and_lane_settings() local
325 for (lane = 0; lane < in dpcd_set_lt_pattern_and_lane_settings()
326 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
328 dpcd_lane[lane].bits.VOLTAGE_SWING_SET = in dpcd_set_lt_pattern_and_lane_settings()
329 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING); in dpcd_set_lt_pattern_and_lane_settings()
330 dpcd_lane[lane].bits.PRE_EMPHASIS_SET = in dpcd_set_lt_pattern_and_lane_settings()
331 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS); in dpcd_set_lt_pattern_and_lane_settings()
333 dpcd_lane[lane].bits.MAX_SWING_REACHED = in dpcd_set_lt_pattern_and_lane_settings()
334 (lt_settings->lane_settings[lane].VOLTAGE_SWING == in dpcd_set_lt_pattern_and_lane_settings()
336 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = in dpcd_set_lt_pattern_and_lane_settings()
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/Linux-v5.10/drivers/phy/rockchip/
Dphy-rockchip-typec.c505 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
511 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
512 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
515 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
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/Linux-v5.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
/Linux-v5.10/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
/Linux-v5.10/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
283 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr() argument
289 serdes_regs, lane + 1, 5); in netcp_xgbe_serdes_reset_cdr()
298 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + in netcp_xgbe_serdes_reset_cdr()
430 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2() argument
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/Linux-v5.10/drivers/pinctrl/tegra/
Dpinctrl-tegra-xusb.c299 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinmux_set() local
303 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
305 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_pinmux_set()
306 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
309 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
312 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinmux_set()
313 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
314 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
315 padctl_writel(padctl, value, lane->offset); in tegra_xusb_padctl_pinmux_set()
332 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_get() local
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/Linux-v5.10/drivers/ata/
Dsata_highbank.c259 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_disable_overrides() local
263 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in highbank_cphy_disable_overrides()
265 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in highbank_cphy_disable_overrides()
270 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_tx_attenuation() local
276 tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_override_tx_attenuation()
278 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
281 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
284 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
289 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_rx_mode() local
291 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_override_rx_mode()
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/Linux-v5.10/drivers/thunderbolt/
Dlc.c52 u32 ctrl, lane; in tb_lc_set_port_configured() local
68 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
70 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
73 ctrl |= lane; in tb_lc_set_port_configured()
77 ctrl &= ~lane; in tb_lc_set_port_configured()
110 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
126 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
128 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
131 ctrl |= lane; in tb_lc_set_xdomain_configured()
133 ctrl &= ~lane; in tb_lc_set_xdomain_configured()
/Linux-v5.10/drivers/nvdimm/
Dbtt.c206 static int btt_log_group_read(struct arena_info *arena, u32 lane, in btt_log_group_read() argument
210 arena->logoff + (lane * LOG_GRP_SIZE), log, in btt_log_group_read()
327 static int btt_log_read(struct arena_info *arena, u32 lane, in btt_log_read() argument
334 ret = btt_log_group_read(arena, lane, &log); in btt_log_read()
342 old_ent, lane, log.ent[arena->log_index[0]].seq, in btt_log_read()
361 static int __btt_log_write(struct arena_info *arena, u32 lane, in __btt_log_write() argument
370 ns_off = arena->logoff + (lane * LOG_GRP_SIZE) + in __btt_log_write()
382 static int btt_flog_write(struct arena_info *arena, u32 lane, u32 sub, in btt_flog_write() argument
387 ret = __btt_log_write(arena, lane, sub, ent, NVDIMM_IO_ATOMIC); in btt_flog_write()
392 arena->freelist[lane].sub = 1 - arena->freelist[lane].sub; in btt_flog_write()
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/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.txt29 Each group of PHY lanes with a single master lane should be represented as
30 a sub-node. Note that the actual configuration of each lane is determined by
35 - reg: The master lane number. This is the lowest numbered lane
36 in the lane group.
38 master lane of the sub-node.
/Linux-v5.10/drivers/phy/xilinx/
Dphy-zynqmp.c196 u8 lane; member
275 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
284 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
293 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
331 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
345 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
349 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
351 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
391 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
439 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
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