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Searched refs:ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h13395 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_1_0_offset.h13635 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_2_0_0_offset.h17059 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_0_0_offset.h17401 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h17448 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro