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Searched refs:intel_de_posting_read (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/i915/display/
Dintel_fifo_underrun.c103 intel_de_posting_read(dev_priv, reg); in i9xx_check_fifo_underruns()
123 intel_de_posting_read(dev_priv, reg); in i9xx_set_fifo_underrun_reporting()
156 intel_de_posting_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
225 intel_de_posting_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
Dintel_hdmi.c245 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
320 intel_de_posting_read(dev_priv, reg); in ibx_write_infoframe()
402 intel_de_posting_read(dev_priv, reg); in cpt_write_infoframe()
478 intel_de_posting_read(dev_priv, reg); in vlv_write_infoframe()
555 intel_de_posting_read(dev_priv, ctl_reg); in hsw_write_infoframe()
906 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
926 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
1078 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1099 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1135 intel_de_posting_read(dev_priv, reg); in cpt_set_infoframes()
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Dintel_de.h20 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_posting_read() function
Dintel_dsb.c57 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_enable_engine()
75 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_disable_engine()
Dintel_pipe_crc.c618 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); in intel_crtc_set_crc_source()
653 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); in intel_crtc_enable_pipe_crc()
668 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); in intel_crtc_disable_pipe_crc()
Dintel_dpll_mgr.c460 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
469 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
479 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_disable()
559 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
567 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_enable()
579 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
597 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
1176 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1189 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1190 intel_de_posting_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_enable()
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Dintel_vga.c41 intel_de_posting_read(dev_priv, vga_reg); in intel_vga_disable()
Dintel_dp.c847 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
850 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
853 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
3027 intel_de_posting_read(dev_priv, pp_ctrl_reg); in edp_panel_vdd_on()
3094 intel_de_posting_read(dev_priv, pp_ctrl_reg); in edp_panel_vdd_off_sync()
3189 intel_de_posting_read(dev_priv, pp_ctrl_reg); in edp_panel_on()
3197 intel_de_posting_read(dev_priv, pp_ctrl_reg); in edp_panel_on()
3205 intel_de_posting_read(dev_priv, pp_ctrl_reg); in edp_panel_on()
3251 intel_de_posting_read(dev_priv, pp_ctrl_reg); in edp_panel_off()
3293 intel_de_posting_read(dev_priv, pp_ctrl_reg); in _intel_edp_backlight_on()
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Dintel_ddi.c1408 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1436 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1446 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1455 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1478 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1483 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1490 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1499 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
2886 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2944 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); in icl_map_plls_to_ports()
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Dintel_panel.c921 intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
957 intel_de_posting_read(dev_priv, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
971 intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
1001 intel_de_posting_read(dev_priv, BLC_PWM_CTL); in i9xx_enable_backlight()
1044 intel_de_posting_read(dev_priv, BLC_PWM_CTL2); in i965_enable_backlight()
1076 intel_de_posting_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
1129 intel_de_posting_read(dev_priv, in bxt_enable_backlight()
1165 intel_de_posting_read(dev_priv, in cnp_enable_backlight()
Dintel_display.c1405 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in vlv_enable_pll()
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in chv_enable_pll()
1534 intel_de_posting_read(dev_priv, reg); in i9xx_enable_pll()
1552 intel_de_posting_read(dev_priv, reg); in i9xx_enable_pll()
1571 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
1587 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
1604 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
1891 intel_de_posting_read(dev_priv, reg); in intel_enable_pipe()
5105 intel_de_posting_read(dev_priv, reg); in intel_fdi_normal_train()
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Dintel_lvds.c319 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
344 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
Dintel_crt.c481 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
958 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
Dvlv_dsi_pll.c519 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
Dintel_csr.c288 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); in gen9_set_dc_state_debugmask()
Dicl_dsi.c344 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
350 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
656 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
Dintel_sdvo.c222 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
229 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
246 intel_de_posting_read(dev_priv, GEN3_SDVOB); in intel_sdvo_write_sdvox()
249 intel_de_posting_read(dev_priv, GEN3_SDVOC); in intel_sdvo_write_sdvox()
Dintel_cdclk.c985 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
1079 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1094 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
Dintel_tv.c1619 intel_de_posting_read(dev_priv, TV_DAC); in intel_tv_detect_type()
1651 intel_de_posting_read(dev_priv, TV_CTL); in intel_tv_detect_type()
Dintel_display_power.c4703 intel_de_posting_read(dev_priv, reg); in gen9_dbuf_slice_set()
4864 intel_de_posting_read(dev_priv, D_COMP_BDW); in hsw_write_dcomp()
4898 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
4916 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
4943 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
Dvlv_dsi.c693 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
712 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
Dintel_fbc.c220 intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); in snb_fbc_recompress()