Home
last modified time | relevance | path

Searched refs:input_clk (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dsnps,hsdk-pll-clock.txt17 input_clk: input-clk {
27 clocks = <&input_clk>;
/Linux-v5.10/drivers/i2c/busses/
Di2c-cadence.c199 unsigned long input_clk; member
965 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument
973 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()
984 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()
990 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
1080 unsigned long input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb() local
1085 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); in cdns_i2c_clk_notifier_cb()
1099 id->input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb()
1234 id->input_clk = clk_get_rate(id->clk); in cdns_i2c_probe()
1248 ret = cdns_i2c_setclk(id->input_clk, id); in cdns_i2c_probe()
/Linux-v5.10/drivers/gpu/drm/nouveau/
Dnouveau_led.c60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness() local
64 div = input_clk / freq; in nouveau_led_set_brightness()
/Linux-v5.10/arch/arc/boot/dts/
Dhsdk.dts62 input_clk: input-clk { label
127 clocks = <&input_clk>;
274 clocks = <&input_clk>;
Daxc003.dtsi24 input_clk: input-clk { label
34 clocks = <&input_clk>;
Daxc003_idu.dtsi24 input_clk: input-clk { label
34 clocks = <&input_clk>;
Daxc001.dtsi31 input_clk: input-clk { label
Daxs10x_mb.dtsi70 clocks = <&input_clk>;
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_hwmgr.c2928 int32_t input_index, input_clk, input_vol, i; in vega20_odn_edit_dpm_table() local
2951 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
2959 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || in vega20_odn_edit_dpm_table()
2960 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { in vega20_odn_edit_dpm_table()
2962 input_clk, in vega20_odn_edit_dpm_table()
2968 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || in vega20_odn_edit_dpm_table()
2969 (input_index == 1 && od_table->GfxclkFmax != input_clk)) in vega20_odn_edit_dpm_table()
2973 od_table->GfxclkFmin = input_clk; in vega20_odn_edit_dpm_table()
2975 od_table->GfxclkFmax = input_clk; in vega20_odn_edit_dpm_table()
2994 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
[all …]
Dsmu7_hwmgr.c4899 uint32_t input_clk; in smu7_odn_edit_dpm_table() local
4940 input_clk = input[i+1] * 100; in smu7_odn_edit_dpm_table()
4943 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in smu7_odn_edit_dpm_table()
4944 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
4945 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
Dvega10_hwmgr.c5245 uint32_t input_clk; in vega10_odn_edit_dpm_table() local
5288 input_clk = input[i+1] * 100; in vega10_odn_edit_dpm_table()
5291 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
5292 dpm_table->dpm_levels[input_level].value = input_clk; in vega10_odn_edit_dpm_table()
5293 podn_vdd_dep_table->entries[input_level].clk = input_clk; in vega10_odn_edit_dpm_table()
/Linux-v5.10/drivers/clk/
Dclk-si5341.c73 struct clk *input_clk[SI5341_NUM_INPUTS]; member
1321 m_den = clk_get_rate(data->input_clk[sel]) / 10; in si5341_initialize_pll()
1340 if (!data->input_clk[res]) { in si5341_clk_select_active_input()
1345 if (data->input_clk[i]) { in si5341_clk_select_active_input()
1362 err = clk_prepare_enable(data->input_clk[res]); in si5341_clk_select_active_input()
1395 data->input_clk[i] = input; in si5341_probe()
/Linux-v5.10/drivers/media/i2c/
Dov5670.c2458 u32 input_clk = 0; in ov5670_probe() local
2461 device_property_read_u32(&client->dev, "clock-frequency", &input_clk); in ov5670_probe()
2462 if (input_clk != 19200000) in ov5670_probe()