1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef ATH11K_DP_H
7 #define ATH11K_DP_H
8
9 #include "hal_rx.h"
10
11 #define MAX_RXDMA_PER_PDEV 2
12
13 struct ath11k_base;
14 struct ath11k_peer;
15 struct ath11k_dp;
16 struct ath11k_vif;
17 struct hal_tcl_status_ring;
18 struct ath11k_ext_irq_grp;
19
20 struct dp_rx_tid {
21 u8 tid;
22 u32 *vaddr;
23 dma_addr_t paddr;
24 u32 size;
25 u32 ba_win_sz;
26 bool active;
27
28 /* Info related to rx fragments */
29 u32 cur_sn;
30 u16 last_frag_no;
31 u16 rx_frag_bitmap;
32
33 struct sk_buff_head rx_frags;
34 struct hal_reo_dest_ring *dst_ring_desc;
35
36 /* Timer info related to fragments */
37 struct timer_list frag_timer;
38 struct ath11k_base *ab;
39 };
40
41 #define DP_REO_DESC_FREE_THRESHOLD 64
42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
43 #define DP_MON_SERVICE_BUDGET 128
44
45 struct dp_reo_cache_flush_elem {
46 struct list_head list;
47 struct dp_rx_tid data;
48 unsigned long ts;
49 };
50
51 struct dp_reo_cmd {
52 struct list_head list;
53 struct dp_rx_tid data;
54 int cmd_num;
55 void (*handler)(struct ath11k_dp *, void *,
56 enum hal_reo_cmd_status status);
57 };
58
59 struct dp_srng {
60 u32 *vaddr_unaligned;
61 u32 *vaddr;
62 dma_addr_t paddr_unaligned;
63 dma_addr_t paddr;
64 int size;
65 u32 ring_id;
66 };
67
68 struct dp_rxdma_ring {
69 struct dp_srng refill_buf_ring;
70 struct idr bufs_idr;
71 /* Protects bufs_idr */
72 spinlock_t idr_lock;
73 int bufs_max;
74 };
75
76 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE)
77
78 struct dp_tx_ring {
79 u8 tcl_data_ring_id;
80 struct dp_srng tcl_data_ring;
81 struct dp_srng tcl_comp_ring;
82 struct idr txbuf_idr;
83 /* Protects txbuf_idr and num_pending */
84 spinlock_t tx_idr_lock;
85 struct hal_wbm_release_ring *tx_status;
86 int tx_status_head;
87 int tx_status_tail;
88 };
89
90 struct ath11k_pdev_mon_stats {
91 u32 status_ppdu_state;
92 u32 status_ppdu_start;
93 u32 status_ppdu_end;
94 u32 status_ppdu_compl;
95 u32 status_ppdu_start_mis;
96 u32 status_ppdu_end_mis;
97 u32 status_ppdu_done;
98 u32 dest_ppdu_done;
99 u32 dest_mpdu_done;
100 u32 dest_mpdu_drop;
101 u32 dup_mon_linkdesc_cnt;
102 u32 dup_mon_buf_cnt;
103 };
104
105 struct dp_link_desc_bank {
106 void *vaddr_unaligned;
107 void *vaddr;
108 dma_addr_t paddr_unaligned;
109 dma_addr_t paddr;
110 u32 size;
111 };
112
113 /* Size to enforce scatter idle list mode */
114 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
115 #define DP_LINK_DESC_BANKS_MAX 8
116
117 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff
118 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000
119 #define DP_RX_DESC_COOKIE_MAX \
120 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
121 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
122
123 enum ath11k_dp_ppdu_state {
124 DP_PPDU_STATUS_START,
125 DP_PPDU_STATUS_DONE,
126 };
127
128 struct ath11k_mon_data {
129 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
130 struct hal_rx_mon_ppdu_info mon_ppdu_info;
131
132 u32 mon_ppdu_status;
133 u32 mon_last_buf_cookie;
134 u64 mon_last_linkdesc_paddr;
135 u16 chan_noise_floor;
136
137 struct ath11k_pdev_mon_stats rx_mon_stats;
138 /* lock for monitor data */
139 spinlock_t mon_lock;
140 struct sk_buff_head rx_status_q;
141 };
142
143 struct ath11k_pdev_dp {
144 u32 mac_id;
145 atomic_t num_tx_pending;
146 wait_queue_head_t tx_empty_waitq;
147 struct dp_rxdma_ring rx_refill_buf_ring;
148 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
149 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
150 struct dp_srng rxdma_mon_dst_ring;
151 struct dp_srng rxdma_mon_desc_ring;
152
153 struct dp_rxdma_ring rxdma_mon_buf_ring;
154 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
155 struct ieee80211_rx_status rx_status;
156 struct ath11k_mon_data mon_data;
157 };
158
159 #define DP_NUM_CLIENTS_MAX 64
160 #define DP_AVG_TIDS_PER_CLIENT 2
161 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
162 #define DP_AVG_MSDUS_PER_FLOW 128
163 #define DP_AVG_FLOWS_PER_TID 2
164 #define DP_AVG_MPDUS_PER_TID_MAX 128
165 #define DP_AVG_MSDUS_PER_MPDU 4
166
167 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
168
169 #define DP_BA_WIN_SZ_MAX 256
170
171 #define DP_TCL_NUM_RING_MAX 3
172
173 #define DP_IDLE_SCATTER_BUFS_MAX 16
174
175 #define DP_WBM_RELEASE_RING_SIZE 64
176 #define DP_TCL_DATA_RING_SIZE 512
177 #define DP_TX_COMP_RING_SIZE 32768
178 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
179 #define DP_TCL_CMD_RING_SIZE 32
180 #define DP_TCL_STATUS_RING_SIZE 32
181 #define DP_REO_DST_RING_MAX 4
182 #define DP_REO_DST_RING_SIZE 2048
183 #define DP_REO_REINJECT_RING_SIZE 32
184 #define DP_RX_RELEASE_RING_SIZE 1024
185 #define DP_REO_EXCEPTION_RING_SIZE 128
186 #define DP_REO_CMD_RING_SIZE 128
187 #define DP_REO_STATUS_RING_SIZE 2048
188 #define DP_RXDMA_BUF_RING_SIZE 4096
189 #define DP_RXDMA_REFILL_RING_SIZE 2048
190 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
191 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
192 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
193 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
194 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
195
196 #define DP_RX_BUFFER_SIZE 2048
197 #define DP_RX_BUFFER_ALIGN_SIZE 128
198
199 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
200 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
201
202 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
203 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
204
205 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
206 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
207 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
208
209 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
210 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
211
212 struct ath11k_hp_update_timer {
213 struct timer_list timer;
214 bool started;
215 bool init;
216 u32 tx_num;
217 u32 timer_tx_num;
218 u32 ring_id;
219 u32 interval;
220 struct ath11k_base *ab;
221 };
222
223 struct ath11k_dp {
224 struct ath11k_base *ab;
225 enum ath11k_htc_ep_id eid;
226 struct completion htt_tgt_version_received;
227 u8 htt_tgt_ver_major;
228 u8 htt_tgt_ver_minor;
229 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
230 struct dp_srng wbm_idle_ring;
231 struct dp_srng wbm_desc_rel_ring;
232 struct dp_srng tcl_cmd_ring;
233 struct dp_srng tcl_status_ring;
234 struct dp_srng reo_reinject_ring;
235 struct dp_srng rx_rel_ring;
236 struct dp_srng reo_except_ring;
237 struct dp_srng reo_cmd_ring;
238 struct dp_srng reo_status_ring;
239 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
240 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
241 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
242 struct list_head reo_cmd_list;
243 struct list_head reo_cmd_cache_flush_list;
244 u32 reo_cmd_cache_flush_count;
245 /**
246 * protects access to below fields,
247 * - reo_cmd_list
248 * - reo_cmd_cache_flush_list
249 * - reo_cmd_cache_flush_count
250 */
251 spinlock_t reo_cmd_lock;
252 struct ath11k_hp_update_timer reo_cmd_timer;
253 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
254 };
255
256 /* HTT definitions */
257
258 #define HTT_TCL_META_DATA_TYPE BIT(0)
259 #define HTT_TCL_META_DATA_VALID_HTT BIT(1)
260
261 /* vdev meta data */
262 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2)
263 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10)
264 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
265
266 /* peer meta data */
267 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2)
268
269 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
270
271 /* HTT tx completion is overlayed in wbm_release_ring */
272 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9)
273 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
274 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13)
275
276 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24)
277
278 struct htt_tx_wbm_completion {
279 u32 info0;
280 u32 info1;
281 u32 info2;
282 u32 info3;
283 } __packed;
284
285 enum htt_h2t_msg_type {
286 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
287 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb,
288 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
289 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
290 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
291 };
292
293 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
294
295 struct htt_ver_req_cmd {
296 u32 ver_reg_info;
297 } __packed;
298
299 enum htt_srng_ring_type {
300 HTT_HW_TO_SW_RING,
301 HTT_SW_TO_HW_RING,
302 HTT_SW_TO_SW_RING,
303 };
304
305 enum htt_srng_ring_id {
306 HTT_RXDMA_HOST_BUF_RING,
307 HTT_RXDMA_MONITOR_STATUS_RING,
308 HTT_RXDMA_MONITOR_BUF_RING,
309 HTT_RXDMA_MONITOR_DESC_RING,
310 HTT_RXDMA_MONITOR_DEST_RING,
311 HTT_HOST1_TO_FW_RXBUF_RING,
312 HTT_HOST2_TO_FW_RXBUF_RING,
313 HTT_RXDMA_NON_MONITOR_DEST_RING,
314 };
315
316 /* host -> target HTT_SRING_SETUP message
317 *
318 * After target is booted up, Host can send SRING setup message for
319 * each host facing LMAC SRING. Target setups up HW registers based
320 * on setup message and confirms back to Host if response_required is set.
321 * Host should wait for confirmation message before sending new SRING
322 * setup message
323 *
324 * The message would appear as follows:
325 *
326 * |31 24|23 20|19|18 16|15|14 8|7 0|
327 * |--------------- +-----------------+----------------+------------------|
328 * | ring_type | ring_id | pdev_id | msg_type |
329 * |----------------------------------------------------------------------|
330 * | ring_base_addr_lo |
331 * |----------------------------------------------------------------------|
332 * | ring_base_addr_hi |
333 * |----------------------------------------------------------------------|
334 * |ring_misc_cfg_flag|ring_entry_size| ring_size |
335 * |----------------------------------------------------------------------|
336 * | ring_head_offset32_remote_addr_lo |
337 * |----------------------------------------------------------------------|
338 * | ring_head_offset32_remote_addr_hi |
339 * |----------------------------------------------------------------------|
340 * | ring_tail_offset32_remote_addr_lo |
341 * |----------------------------------------------------------------------|
342 * | ring_tail_offset32_remote_addr_hi |
343 * |----------------------------------------------------------------------|
344 * | ring_msi_addr_lo |
345 * |----------------------------------------------------------------------|
346 * | ring_msi_addr_hi |
347 * |----------------------------------------------------------------------|
348 * | ring_msi_data |
349 * |----------------------------------------------------------------------|
350 * | intr_timer_th |IM| intr_batch_counter_th |
351 * |----------------------------------------------------------------------|
352 * | reserved |RR|PTCF| intr_low_threshold |
353 * |----------------------------------------------------------------------|
354 * Where
355 * IM = sw_intr_mode
356 * RR = response_required
357 * PTCF = prefetch_timer_cfg
358 *
359 * The message is interpreted as follows:
360 * dword0 - b'0:7 - msg_type: This will be set to
361 * HTT_H2T_MSG_TYPE_SRING_SETUP
362 * b'8:15 - pdev_id:
363 * 0 (for rings at SOC/UMAC level),
364 * 1/2/3 mac id (for rings at LMAC level)
365 * b'16:23 - ring_id: identify which ring is to setup,
366 * more details can be got from enum htt_srng_ring_id
367 * b'24:31 - ring_type: identify type of host rings,
368 * more details can be got from enum htt_srng_ring_type
369 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
370 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
371 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
372 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
373 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
374 * SW_TO_HW_RING.
375 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
376 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
377 * Lower 32 bits of memory address of the remote variable
378 * storing the 4-byte word offset that identifies the head
379 * element within the ring.
380 * (The head offset variable has type u32.)
381 * Valid for HW_TO_SW and SW_TO_SW rings.
382 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
383 * Upper 32 bits of memory address of the remote variable
384 * storing the 4-byte word offset that identifies the head
385 * element within the ring.
386 * (The head offset variable has type u32.)
387 * Valid for HW_TO_SW and SW_TO_SW rings.
388 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
389 * Lower 32 bits of memory address of the remote variable
390 * storing the 4-byte word offset that identifies the tail
391 * element within the ring.
392 * (The tail offset variable has type u32.)
393 * Valid for HW_TO_SW and SW_TO_SW rings.
394 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
395 * Upper 32 bits of memory address of the remote variable
396 * storing the 4-byte word offset that identifies the tail
397 * element within the ring.
398 * (The tail offset variable has type u32.)
399 * Valid for HW_TO_SW and SW_TO_SW rings.
400 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
401 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
402 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
403 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
404 * dword10 - b'0:31 - ring_msi_data: MSI data
405 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
406 * valid only for HW_TO_SW_RING and SW_TO_HW_RING
407 * dword11 - b'0:14 - intr_batch_counter_th:
408 * batch counter threshold is in units of 4-byte words.
409 * HW internally maintains and increments batch count.
410 * (see SRING spec for detail description).
411 * When batch count reaches threshold value, an interrupt
412 * is generated by HW.
413 * b'15 - sw_intr_mode:
414 * This configuration shall be static.
415 * Only programmed at power up.
416 * 0: generate pulse style sw interrupts
417 * 1: generate level style sw interrupts
418 * b'16:31 - intr_timer_th:
419 * The timer init value when timer is idle or is
420 * initialized to start downcounting.
421 * In 8us units (to cover a range of 0 to 524 ms)
422 * dword12 - b'0:15 - intr_low_threshold:
423 * Used only by Consumer ring to generate ring_sw_int_p.
424 * Ring entries low threshold water mark, that is used
425 * in combination with the interrupt timer as well as
426 * the the clearing of the level interrupt.
427 * b'16:18 - prefetch_timer_cfg:
428 * Used only by Consumer ring to set timer mode to
429 * support Application prefetch handling.
430 * The external tail offset/pointer will be updated
431 * at following intervals:
432 * 3'b000: (Prefetch feature disabled; used only for debug)
433 * 3'b001: 1 usec
434 * 3'b010: 4 usec
435 * 3'b011: 8 usec (default)
436 * 3'b100: 16 usec
437 * Others: Reserverd
438 * b'19 - response_required:
439 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
440 * b'20:31 - reserved: reserved for future use
441 */
442
443 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
444 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8)
445 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16)
446 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24)
447
448 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0)
449 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16)
450 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
451 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
452 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
453 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
454
455 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0)
456 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
457 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16)
458
459 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0)
460 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16)
461 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
462
463 struct htt_srng_setup_cmd {
464 u32 info0;
465 u32 ring_base_addr_lo;
466 u32 ring_base_addr_hi;
467 u32 info1;
468 u32 ring_head_off32_remote_addr_lo;
469 u32 ring_head_off32_remote_addr_hi;
470 u32 ring_tail_off32_remote_addr_lo;
471 u32 ring_tail_off32_remote_addr_hi;
472 u32 ring_msi_addr_lo;
473 u32 ring_msi_addr_hi;
474 u32 msi_data;
475 u32 intr_info;
476 u32 info2;
477 } __packed;
478
479 /* host -> target FW PPDU_STATS config message
480 *
481 * @details
482 * The following field definitions describe the format of the HTT host
483 * to target FW for PPDU_STATS_CFG msg.
484 * The message allows the host to configure the PPDU_STATS_IND messages
485 * produced by the target.
486 *
487 * |31 24|23 16|15 8|7 0|
488 * |-----------------------------------------------------------|
489 * | REQ bit mask | pdev_mask | msg type |
490 * |-----------------------------------------------------------|
491 * Header fields:
492 * - MSG_TYPE
493 * Bits 7:0
494 * Purpose: identifies this is a req to configure ppdu_stats_ind from target
495 * Value: 0x11
496 * - PDEV_MASK
497 * Bits 8:15
498 * Purpose: identifies which pdevs this PPDU stats configuration applies to
499 * Value: This is a overloaded field, refer to usage and interpretation of
500 * PDEV in interface document.
501 * Bit 8 : Reserved for SOC stats
502 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
503 * Indicates MACID_MASK in DBS
504 * - REQ_TLV_BIT_MASK
505 * Bits 16:31
506 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
507 * needs to be included in the target's PPDU_STATS_IND messages.
508 * Value: refer htt_ppdu_stats_tlv_tag_t <<<???
509 *
510 */
511
512 struct htt_ppdu_stats_cfg_cmd {
513 u32 msg;
514 } __packed;
515
516 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0)
517 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8)
518 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16)
519
520 enum htt_ppdu_stats_tag_type {
521 HTT_PPDU_STATS_TAG_COMMON,
522 HTT_PPDU_STATS_TAG_USR_COMMON,
523 HTT_PPDU_STATS_TAG_USR_RATE,
524 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
525 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
526 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
527 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
528 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
529 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
530 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
531 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
532 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
533 HTT_PPDU_STATS_TAG_INFO,
534 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
535
536 /* New TLV's are added above to this line */
537 HTT_PPDU_STATS_TAG_MAX,
538 };
539
540 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
541 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
542 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
543 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
544 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
545 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
546 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
547 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
548
549 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
550 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
551 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
552 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
553 BIT(HTT_PPDU_STATS_TAG_INFO) | \
554 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
555 HTT_PPDU_STATS_TAG_DEFAULT)
556
557 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
558 *
559 * details:
560 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
561 * configure RXDMA rings.
562 * The configuration is per ring based and includes both packet subtypes
563 * and PPDU/MPDU TLVs.
564 *
565 * The message would appear as follows:
566 *
567 * |31 26|25|24|23 16|15 8|7 0|
568 * |-----------------+----------------+----------------+---------------|
569 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
570 * |-------------------------------------------------------------------|
571 * | rsvd2 | ring_buffer_size |
572 * |-------------------------------------------------------------------|
573 * | packet_type_enable_flags_0 |
574 * |-------------------------------------------------------------------|
575 * | packet_type_enable_flags_1 |
576 * |-------------------------------------------------------------------|
577 * | packet_type_enable_flags_2 |
578 * |-------------------------------------------------------------------|
579 * | packet_type_enable_flags_3 |
580 * |-------------------------------------------------------------------|
581 * | tlv_filter_in_flags |
582 * |-------------------------------------------------------------------|
583 * Where:
584 * PS = pkt_swap
585 * SS = status_swap
586 * The message is interpreted as follows:
587 * dword0 - b'0:7 - msg_type: This will be set to
588 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
589 * b'8:15 - pdev_id:
590 * 0 (for rings at SOC/UMAC level),
591 * 1/2/3 mac id (for rings at LMAC level)
592 * b'16:23 - ring_id : Identify the ring to configure.
593 * More details can be got from enum htt_srng_ring_id
594 * b'24 - status_swap: 1 is to swap status TLV
595 * b'25 - pkt_swap: 1 is to swap packet TLV
596 * b'26:31 - rsvd1: reserved for future use
597 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring,
598 * in byte units.
599 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
600 * - b'16:31 - rsvd2: Reserved for future use
601 * dword2 - b'0:31 - packet_type_enable_flags_0:
602 * Enable MGMT packet from 0b0000 to 0b1001
603 * bits from low to high: FP, MD, MO - 3 bits
604 * FP: Filter_Pass
605 * MD: Monitor_Direct
606 * MO: Monitor_Other
607 * 10 mgmt subtypes * 3 bits -> 30 bits
608 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
609 * dword3 - b'0:31 - packet_type_enable_flags_1:
610 * Enable MGMT packet from 0b1010 to 0b1111
611 * bits from low to high: FP, MD, MO - 3 bits
612 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
613 * dword4 - b'0:31 - packet_type_enable_flags_2:
614 * Enable CTRL packet from 0b0000 to 0b1001
615 * bits from low to high: FP, MD, MO - 3 bits
616 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
617 * dword5 - b'0:31 - packet_type_enable_flags_3:
618 * Enable CTRL packet from 0b1010 to 0b1111,
619 * MCAST_DATA, UCAST_DATA, NULL_DATA
620 * bits from low to high: FP, MD, MO - 3 bits
621 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
622 * dword6 - b'0:31 - tlv_filter_in_flags:
623 * Filter in Attention/MPDU/PPDU/Header/User tlvs
624 * Refer to CFG_TLV_FILTER_IN_FLAG defs
625 */
626
627 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
628 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
629 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16)
630 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
631 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
632
633 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0)
634
635 enum htt_rx_filter_tlv_flags {
636 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
637 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
638 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
639 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
640 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
641 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
642 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
643 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
644 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
645 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
646 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
647 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
648 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
649 };
650
651 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
652 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
653 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
654 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
655 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
656 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
657 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
658 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
659 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
660 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
661 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
662 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
663 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
664 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
665 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
666 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
667 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
668 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
669 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
670 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
671 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
672 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
673 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
674 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
675 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
676 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
677 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
678 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
679 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
680 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
681 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
682 };
683
684 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
685 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
686 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
687 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
688 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
689 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
690 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
691 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
692 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
693 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
694 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
695 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
696 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
697 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
698 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
699 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
700 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
701 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
702 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
703 };
704
705 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
706 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
707 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
708 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
709 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
710 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
711 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
712 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
713 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
714 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
715 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
716 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
717 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
718 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
719 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
720 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
721 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
722 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
723 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
724 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
725 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
726 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
727 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
728 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
729 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
730 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
731 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
732 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
733 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
734 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
735 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
736 };
737
738 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
739 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
740 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
741 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
742 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
743 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
744 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
745 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
746 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
747 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
748 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
749 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
750 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
751 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
752 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
753 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
754 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
755 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
756 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
757 };
758
759 enum htt_rx_data_pkt_filter_tlv_flasg3 {
760 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
761 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
762 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
763 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
764 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
765 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
766 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
767 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
768 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
769 };
770
771 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
772 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
773 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
774 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
775 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
776 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
777 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
778 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
779 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
780 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
781
782 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
783 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
784 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
785 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
786 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
787 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
788 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
789 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
790 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
791 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
792
793 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
794 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
795 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
796 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
797 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
798 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
799 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
800 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
801 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
802 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
803
804 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
805 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
806 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
807 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
808 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
809
810 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
811 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
812 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
813 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
814 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
815
816 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
817 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
818 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
819 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
820 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
821
822 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
823 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
824 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
825
826 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
827 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
828 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
829
830 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
831 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
832 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
833
834 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
835 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
836 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
837 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
838 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
839 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
840
841 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
842 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
843 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
844 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
845 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
846 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
847
848 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
849 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
850 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
851 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
852 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
853 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
854
855 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
856 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
857 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
858
859 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
860 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
861 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
862
863 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
864 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
865 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
866
867 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
868 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
869 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
870
871 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
872 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
873 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
874
875 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
876 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
877 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
878
879 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
880 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
881 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
882
883 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
884 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \
885 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
886 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
888 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
889 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
891 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
892
893 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
894 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \
895 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
896 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
897 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
899 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
900 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
902
903 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
904
905 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
906
907 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
908
909 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
910
911 #define HTT_RX_MON_FILTER_TLV_FLAGS \
912 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
913 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
914 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
915 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
916 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
917 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
918
919 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
920 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
921 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
922 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
923 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
924 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
925 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
926
927 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
928 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
929 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
930 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
931 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
932 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
933 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
934 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
935 HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
936
937 struct htt_rx_ring_selection_cfg_cmd {
938 u32 info0;
939 u32 info1;
940 u32 pkt_type_en_flags0;
941 u32 pkt_type_en_flags1;
942 u32 pkt_type_en_flags2;
943 u32 pkt_type_en_flags3;
944 u32 rx_filter_tlv;
945 } __packed;
946
947 struct htt_rx_ring_tlv_filter {
948 u32 rx_filter; /* see htt_rx_filter_tlv_flags */
949 u32 pkt_filter_flags0; /* MGMT */
950 u32 pkt_filter_flags1; /* MGMT */
951 u32 pkt_filter_flags2; /* CTRL */
952 u32 pkt_filter_flags3; /* DATA */
953 };
954
955 /* HTT message target->host */
956
957 enum htt_t2h_msg_type {
958 HTT_T2H_MSG_TYPE_VERSION_CONF,
959 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3,
960 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
961 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5,
962 HTT_T2H_MSG_TYPE_PKTLOG = 0x8,
963 HTT_T2H_MSG_TYPE_SEC_IND = 0xb,
964 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e,
965 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f,
966 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
967 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
968 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
969 };
970
971 #define HTT_TARGET_VERSION_MAJOR 3
972
973 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
974 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8)
975 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16)
976
977 struct htt_t2h_version_conf_msg {
978 u32 version;
979 } __packed;
980
981 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8)
982 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16)
983 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0)
984 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16)
985 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0)
986 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
987 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16
988
989 struct htt_t2h_peer_map_event {
990 u32 info;
991 u32 mac_addr_l32;
992 u32 info1;
993 u32 info2;
994 } __packed;
995
996 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID
997 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID
998 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
999 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1000 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1001 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1002
1003 struct htt_t2h_peer_unmap_event {
1004 u32 info;
1005 u32 mac_addr_l32;
1006 u32 info1;
1007 } __packed;
1008
1009 struct htt_resp_msg {
1010 union {
1011 struct htt_t2h_version_conf_msg version_msg;
1012 struct htt_t2h_peer_map_event peer_map_ev;
1013 struct htt_t2h_peer_unmap_event peer_unmap_ev;
1014 };
1015 } __packed;
1016
1017 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
1018 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
1019 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
1020
1021 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1022 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1023
1024 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0
1025 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1
1026
1027 enum htt_backpressure_umac_ringid {
1028 HTT_SW_RING_IDX_REO_REO2SW1_RING,
1029 HTT_SW_RING_IDX_REO_REO2SW2_RING,
1030 HTT_SW_RING_IDX_REO_REO2SW3_RING,
1031 HTT_SW_RING_IDX_REO_REO2SW4_RING,
1032 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1033 HTT_SW_RING_IDX_REO_REO2TCL_RING,
1034 HTT_SW_RING_IDX_REO_REO2FW_RING,
1035 HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1036 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1037 HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1038 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1039 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1040 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1041 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1042 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1043 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1044 HTT_SW_RING_IDX_REO_REO_CMD_RING,
1045 HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1046 HTT_SW_UMAC_RING_IDX_MAX,
1047 };
1048
1049 enum htt_backpressure_lmac_ringid {
1050 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1051 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1052 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1053 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1054 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1055 HTT_SW_RING_IDX_RXDMA2FW_RING,
1056 HTT_SW_RING_IDX_RXDMA2SW_RING,
1057 HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1058 HTT_SW_RING_IDX_RXDMA2REO_RING,
1059 HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1060 HTT_SW_RING_IDX_MONITOR_BUF_RING,
1061 HTT_SW_RING_IDX_MONITOR_DESC_RING,
1062 HTT_SW_RING_IDX_MONITOR_DEST_RING,
1063 HTT_SW_LMAC_RING_IDX_MAX,
1064 };
1065
1066 /* ppdu stats
1067 *
1068 * @details
1069 * The following field definitions describe the format of the HTT target
1070 * to host ppdu stats indication message.
1071 *
1072 *
1073 * |31 16|15 12|11 10|9 8|7 0 |
1074 * |----------------------------------------------------------------------|
1075 * | payload_size | rsvd |pdev_id|mac_id | msg type |
1076 * |----------------------------------------------------------------------|
1077 * | ppdu_id |
1078 * |----------------------------------------------------------------------|
1079 * | Timestamp in us |
1080 * |----------------------------------------------------------------------|
1081 * | reserved |
1082 * |----------------------------------------------------------------------|
1083 * | type-specific stats info |
1084 * | (see htt_ppdu_stats.h) |
1085 * |----------------------------------------------------------------------|
1086 * Header fields:
1087 * - MSG_TYPE
1088 * Bits 7:0
1089 * Purpose: Identifies this is a PPDU STATS indication
1090 * message.
1091 * Value: 0x1d
1092 * - mac_id
1093 * Bits 9:8
1094 * Purpose: mac_id of this ppdu_id
1095 * Value: 0-3
1096 * - pdev_id
1097 * Bits 11:10
1098 * Purpose: pdev_id of this ppdu_id
1099 * Value: 0-3
1100 * 0 (for rings at SOC level),
1101 * 1/2/3 PDEV -> 0/1/2
1102 * - payload_size
1103 * Bits 31:16
1104 * Purpose: total tlv size
1105 * Value: payload_size in bytes
1106 */
1107
1108 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1109 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1110
1111 struct ath11k_htt_ppdu_stats_msg {
1112 u32 info;
1113 u32 ppdu_id;
1114 u32 timestamp;
1115 u32 rsvd;
1116 u8 data[0];
1117 } __packed;
1118
1119 struct htt_tlv {
1120 u32 header;
1121 u8 value[0];
1122 } __packed;
1123
1124 #define HTT_TLV_TAG GENMASK(11, 0)
1125 #define HTT_TLV_LEN GENMASK(23, 12)
1126
1127 enum HTT_PPDU_STATS_BW {
1128 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0,
1129 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1,
1130 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2,
1131 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1132 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
1133 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1134 HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
1135 };
1136
1137 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0)
1138 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8)
1139 /* bw - HTT_PPDU_STATS_BW */
1140 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16)
1141
1142 struct htt_ppdu_stats_common {
1143 u32 ppdu_id;
1144 u16 sched_cmdid;
1145 u8 ring_id;
1146 u8 num_users;
1147 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1148 u32 chain_mask;
1149 u32 fes_duration_us; /* frame exchange sequence */
1150 u32 ppdu_sch_eval_start_tstmp_us;
1151 u32 ppdu_sch_end_tstmp_us;
1152 u32 ppdu_start_tstmp_us;
1153 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1154 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1155 */
1156 u16 phy_mode;
1157 u16 bw_mhz;
1158 } __packed;
1159
1160 enum htt_ppdu_stats_gi {
1161 HTT_PPDU_STATS_SGI_0_8_US,
1162 HTT_PPDU_STATS_SGI_0_4_US,
1163 HTT_PPDU_STATS_SGI_1_6_US,
1164 HTT_PPDU_STATS_SGI_3_2_US,
1165 };
1166
1167 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1168 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4)
1169
1170 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1171 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1)
1172
1173 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1174 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1175 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1176 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4)
1177 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8)
1178 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12)
1179 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16)
1180 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1181 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24)
1182 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1183 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1184
1185 #define HTT_USR_RATE_PREAMBLE(_val) \
1186 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1187 #define HTT_USR_RATE_BW(_val) \
1188 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1189 #define HTT_USR_RATE_NSS(_val) \
1190 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1191 #define HTT_USR_RATE_MCS(_val) \
1192 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1193 #define HTT_USR_RATE_GI(_val) \
1194 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1195 #define HTT_USR_RATE_DCM(_val) \
1196 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1197
1198 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0)
1199 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1200 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1201 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4)
1202 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8)
1203 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12)
1204 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16)
1205 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
1206 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24)
1207 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1208 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1209
1210 struct htt_ppdu_stats_user_rate {
1211 u8 tid_num;
1212 u8 reserved0;
1213 u16 sw_peer_id;
1214 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1215 u16 ru_end;
1216 u16 ru_start;
1217 u16 resp_ru_end;
1218 u16 resp_ru_start;
1219 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1220 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1221 /* Note: resp_rate_info is only valid for if resp_type is UL */
1222 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1223 } __packed;
1224
1225 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0)
1226 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1227 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9)
1228 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11)
1229 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1230 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16)
1231
1232 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1233 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1234 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1235 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1236 #define HTT_TX_INFO_RATECODE(_flags) \
1237 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1238 #define HTT_TX_INFO_PEERID(_flags) \
1239 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1240
1241 struct htt_tx_ppdu_stats_info {
1242 struct htt_tlv tlv_hdr;
1243 u32 tx_success_bytes;
1244 u32 tx_retry_bytes;
1245 u32 tx_failed_bytes;
1246 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1247 u16 tx_success_msdus;
1248 u16 tx_retry_msdus;
1249 u16 tx_failed_msdus;
1250 u16 tx_duration; /* united in us */
1251 } __packed;
1252
1253 enum htt_ppdu_stats_usr_compln_status {
1254 HTT_PPDU_STATS_USER_STATUS_OK,
1255 HTT_PPDU_STATS_USER_STATUS_FILTERED,
1256 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1257 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1258 HTT_PPDU_STATS_USER_STATUS_ABORT,
1259 };
1260
1261 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1262 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4)
1263 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1264 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9)
1265
1266 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1267 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1268 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1269 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1270 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1271 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1272
1273 struct htt_ppdu_stats_usr_cmpltn_cmn {
1274 u8 status;
1275 u8 tid_num;
1276 u16 sw_peer_id;
1277 /* RSSI value of last ack packet (units = dB above noise floor) */
1278 u32 ack_rssi;
1279 u16 mpdu_tried;
1280 u16 mpdu_success;
1281 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1282 } __packed;
1283
1284 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0)
1285 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9)
1286 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25)
1287
1288 #define HTT_PPDU_STATS_NON_QOS_TID 16
1289
1290 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1291 u32 ppdu_id;
1292 u16 sw_peer_id;
1293 u16 reserved0;
1294 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1295 u16 current_seq;
1296 u16 start_seq;
1297 u32 success_bytes;
1298 } __packed;
1299
1300 struct htt_ppdu_stats_usr_cmn_array {
1301 struct htt_tlv tlv_hdr;
1302 u32 num_ppdu_stats;
1303 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info
1304 * elements.
1305 * tx_ppdu_stats_info is variable length, with length =
1306 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
1307 */
1308 struct htt_tx_ppdu_stats_info tx_ppdu_info[0];
1309 } __packed;
1310
1311 struct htt_ppdu_user_stats {
1312 u16 peer_id;
1313 u32 tlv_flags;
1314 bool is_valid_peer_id;
1315 struct htt_ppdu_stats_user_rate rate;
1316 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1317 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1318 };
1319
1320 #define HTT_PPDU_STATS_MAX_USERS 8
1321 #define HTT_PPDU_DESC_MAX_DEPTH 16
1322
1323 struct htt_ppdu_stats {
1324 struct htt_ppdu_stats_common common;
1325 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1326 };
1327
1328 struct htt_ppdu_stats_info {
1329 u32 ppdu_id;
1330 struct htt_ppdu_stats ppdu_stats;
1331 struct list_head list;
1332 };
1333
1334 /**
1335 * @brief target -> host packet log message
1336 *
1337 * @details
1338 * The following field definitions describe the format of the packet log
1339 * message sent from the target to the host.
1340 * The message consists of a 4-octet header,followed by a variable number
1341 * of 32-bit character values.
1342 *
1343 * |31 16|15 12|11 10|9 8|7 0|
1344 * |------------------------------------------------------------------|
1345 * | payload_size | rsvd |pdev_id|mac_id| msg type |
1346 * |------------------------------------------------------------------|
1347 * | payload |
1348 * |------------------------------------------------------------------|
1349 * - MSG_TYPE
1350 * Bits 7:0
1351 * Purpose: identifies this as a pktlog message
1352 * Value: HTT_T2H_MSG_TYPE_PKTLOG
1353 * - mac_id
1354 * Bits 9:8
1355 * Purpose: identifies which MAC/PHY instance generated this pktlog info
1356 * Value: 0-3
1357 * - pdev_id
1358 * Bits 11:10
1359 * Purpose: pdev_id
1360 * Value: 0-3
1361 * 0 (for rings at SOC level),
1362 * 1/2/3 PDEV -> 0/1/2
1363 * - payload_size
1364 * Bits 31:16
1365 * Purpose: explicitly specify the payload size
1366 * Value: payload size in bytes (payload size is a multiple of 4 bytes)
1367 */
1368 struct htt_pktlog_msg {
1369 u32 hdr;
1370 u8 payload[0];
1371 };
1372
1373 /**
1374 * @brief host -> target FW extended statistics retrieve
1375 *
1376 * @details
1377 * The following field definitions describe the format of the HTT host
1378 * to target FW extended stats retrieve message.
1379 * The message specifies the type of stats the host wants to retrieve.
1380 *
1381 * |31 24|23 16|15 8|7 0|
1382 * |-----------------------------------------------------------|
1383 * | reserved | stats type | pdev_mask | msg type |
1384 * |-----------------------------------------------------------|
1385 * | config param [0] |
1386 * |-----------------------------------------------------------|
1387 * | config param [1] |
1388 * |-----------------------------------------------------------|
1389 * | config param [2] |
1390 * |-----------------------------------------------------------|
1391 * | config param [3] |
1392 * |-----------------------------------------------------------|
1393 * | reserved |
1394 * |-----------------------------------------------------------|
1395 * | cookie LSBs |
1396 * |-----------------------------------------------------------|
1397 * | cookie MSBs |
1398 * |-----------------------------------------------------------|
1399 * Header fields:
1400 * - MSG_TYPE
1401 * Bits 7:0
1402 * Purpose: identifies this is a extended stats upload request message
1403 * Value: 0x10
1404 * - PDEV_MASK
1405 * Bits 8:15
1406 * Purpose: identifies the mask of PDEVs to retrieve stats from
1407 * Value: This is a overloaded field, refer to usage and interpretation of
1408 * PDEV in interface document.
1409 * Bit 8 : Reserved for SOC stats
1410 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1411 * Indicates MACID_MASK in DBS
1412 * - STATS_TYPE
1413 * Bits 23:16
1414 * Purpose: identifies which FW statistics to upload
1415 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1416 * - Reserved
1417 * Bits 31:24
1418 * - CONFIG_PARAM [0]
1419 * Bits 31:0
1420 * Purpose: give an opaque configuration value to the specified stats type
1421 * Value: stats-type specific configuration value
1422 * Refer to htt_stats.h for interpretation for each stats sub_type
1423 * - CONFIG_PARAM [1]
1424 * Bits 31:0
1425 * Purpose: give an opaque configuration value to the specified stats type
1426 * Value: stats-type specific configuration value
1427 * Refer to htt_stats.h for interpretation for each stats sub_type
1428 * - CONFIG_PARAM [2]
1429 * Bits 31:0
1430 * Purpose: give an opaque configuration value to the specified stats type
1431 * Value: stats-type specific configuration value
1432 * Refer to htt_stats.h for interpretation for each stats sub_type
1433 * - CONFIG_PARAM [3]
1434 * Bits 31:0
1435 * Purpose: give an opaque configuration value to the specified stats type
1436 * Value: stats-type specific configuration value
1437 * Refer to htt_stats.h for interpretation for each stats sub_type
1438 * - Reserved [31:0] for future use.
1439 * - COOKIE_LSBS
1440 * Bits 31:0
1441 * Purpose: Provide a mechanism to match a target->host stats confirmation
1442 * message with its preceding host->target stats request message.
1443 * Value: LSBs of the opaque cookie specified by the host-side requestor
1444 * - COOKIE_MSBS
1445 * Bits 31:0
1446 * Purpose: Provide a mechanism to match a target->host stats confirmation
1447 * message with its preceding host->target stats request message.
1448 * Value: MSBs of the opaque cookie specified by the host-side requestor
1449 */
1450
1451 struct htt_ext_stats_cfg_hdr {
1452 u8 msg_type;
1453 u8 pdev_mask;
1454 u8 stats_type;
1455 u8 reserved;
1456 } __packed;
1457
1458 struct htt_ext_stats_cfg_cmd {
1459 struct htt_ext_stats_cfg_hdr hdr;
1460 u32 cfg_param0;
1461 u32 cfg_param1;
1462 u32 cfg_param2;
1463 u32 cfg_param3;
1464 u32 reserved;
1465 u32 cookie_lsb;
1466 u32 cookie_msb;
1467 } __packed;
1468
1469 /* htt stats config default params */
1470 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1471 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1472 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1473 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1474 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1475 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1476 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1477 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1478
1479 /* HTT_DBG_EXT_STATS_PEER_INFO
1480 * PARAMS:
1481 * @config_param0:
1482 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1483 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1484 * [Bit31 : Bit16] sw_peer_id
1485 * @config_param1:
1486 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1487 * 0 bit htt_peer_stats_cmn_tlv
1488 * 1 bit htt_peer_details_tlv
1489 * 2 bit htt_tx_peer_rate_stats_tlv
1490 * 3 bit htt_rx_peer_rate_stats_tlv
1491 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1492 * 5 bit htt_rx_tid_stats_tlv
1493 * 6 bit htt_msdu_flow_stats_tlv
1494 * @config_param2: [Bit31 : Bit0] mac_addr31to0
1495 * @config_param3: [Bit15 : Bit0] mac_addr47to32
1496 * [Bit31 : Bit16] reserved
1497 */
1498 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1499 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1500
1501 /* Used to set different configs to the specified stats type.*/
1502 struct htt_ext_stats_cfg_params {
1503 u32 cfg0;
1504 u32 cfg1;
1505 u32 cfg2;
1506 u32 cfg3;
1507 };
1508
1509 /**
1510 * @brief target -> host extended statistics upload
1511 *
1512 * @details
1513 * The following field definitions describe the format of the HTT target
1514 * to host stats upload confirmation message.
1515 * The message contains a cookie echoed from the HTT host->target stats
1516 * upload request, which identifies which request the confirmation is
1517 * for, and a single stats can span over multiple HTT stats indication
1518 * due to the HTT message size limitation so every HTT ext stats indication
1519 * will have tag-length-value stats information elements.
1520 * The tag-length header for each HTT stats IND message also includes a
1521 * status field, to indicate whether the request for the stat type in
1522 * question was fully met, partially met, unable to be met, or invalid
1523 * (if the stat type in question is disabled in the target).
1524 * A Done bit 1's indicate the end of the of stats info elements.
1525 *
1526 *
1527 * |31 16|15 12|11|10 8|7 5|4 0|
1528 * |--------------------------------------------------------------|
1529 * | reserved | msg type |
1530 * |--------------------------------------------------------------|
1531 * | cookie LSBs |
1532 * |--------------------------------------------------------------|
1533 * | cookie MSBs |
1534 * |--------------------------------------------------------------|
1535 * | stats entry length | rsvd | D| S | stat type |
1536 * |--------------------------------------------------------------|
1537 * | type-specific stats info |
1538 * | (see htt_stats.h) |
1539 * |--------------------------------------------------------------|
1540 * Header fields:
1541 * - MSG_TYPE
1542 * Bits 7:0
1543 * Purpose: Identifies this is a extended statistics upload confirmation
1544 * message.
1545 * Value: 0x1c
1546 * - COOKIE_LSBS
1547 * Bits 31:0
1548 * Purpose: Provide a mechanism to match a target->host stats confirmation
1549 * message with its preceding host->target stats request message.
1550 * Value: LSBs of the opaque cookie specified by the host-side requestor
1551 * - COOKIE_MSBS
1552 * Bits 31:0
1553 * Purpose: Provide a mechanism to match a target->host stats confirmation
1554 * message with its preceding host->target stats request message.
1555 * Value: MSBs of the opaque cookie specified by the host-side requestor
1556 *
1557 * Stats Information Element tag-length header fields:
1558 * - STAT_TYPE
1559 * Bits 7:0
1560 * Purpose: identifies the type of statistics info held in the
1561 * following information element
1562 * Value: htt_dbg_ext_stats_type
1563 * - STATUS
1564 * Bits 10:8
1565 * Purpose: indicate whether the requested stats are present
1566 * Value: htt_dbg_ext_stats_status
1567 * - DONE
1568 * Bits 11
1569 * Purpose:
1570 * Indicates the completion of the stats entry, this will be the last
1571 * stats conf HTT segment for the requested stats type.
1572 * Value:
1573 * 0 -> the stats retrieval is ongoing
1574 * 1 -> the stats retrieval is complete
1575 * - LENGTH
1576 * Bits 31:16
1577 * Purpose: indicate the stats information size
1578 * Value: This field specifies the number of bytes of stats information
1579 * that follows the element tag-length header.
1580 * It is expected but not required that this length is a multiple of
1581 * 4 bytes.
1582 */
1583
1584 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
1585 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
1586
1587 struct ath11k_htt_extd_stats_msg {
1588 u32 info0;
1589 u64 cookie;
1590 u32 info1;
1591 u8 data[0];
1592 } __packed;
1593
1594 struct htt_mac_addr {
1595 u32 mac_addr_l32;
1596 u32 mac_addr_h16;
1597 };
1598
ath11k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1599 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1600 {
1601 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1602 addr_l32 = swab32(addr_l32);
1603 addr_h16 = swab16(addr_h16);
1604 }
1605
1606 memcpy(addr, &addr_l32, 4);
1607 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1608 }
1609
1610 int ath11k_dp_service_srng(struct ath11k_base *ab,
1611 struct ath11k_ext_irq_grp *irq_grp,
1612 int budget);
1613 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1614 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1615 void ath11k_dp_free(struct ath11k_base *ab);
1616 int ath11k_dp_alloc(struct ath11k_base *ab);
1617 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1618 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1619 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1620 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1621 int mac_id, enum hal_ring_type ring_type);
1622 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1623 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1624 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1625 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1626 enum hal_ring_type type, int ring_num,
1627 int mac_id, int num_entries);
1628 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1629 struct dp_link_desc_bank *desc_bank,
1630 u32 ring_type, struct dp_srng *ring);
1631 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1632 struct dp_link_desc_bank *link_desc_banks,
1633 u32 ring_type, struct hal_srng *srng,
1634 u32 n_link_desc);
1635 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1636 struct hal_srng *srng,
1637 struct ath11k_hp_update_timer *update_timer);
1638 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1639 struct ath11k_hp_update_timer *update_timer);
1640 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1641 struct ath11k_hp_update_timer *update_timer,
1642 u32 interval, u32 ring_id);
1643
1644 #endif
1645
