Searched refs:engineClock (Results 1 – 14 of 14) sorted by relevance
210 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; in init_powerplay_table_information()212 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_powerplay_table_information()230 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_powerplay_table_information()
417 data->boot_power_level.engineClock = in smu8_construct_boot_state()1343 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()1345 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()1379 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()1599 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()1603 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()1604 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()1627 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()1628 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1]… in smu8_get_current_shallow_sleep_clocks()
100 uint32_t engineClock; member
910 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()1354 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()1355 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()1565 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()3214 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()3245 minimum_clocks.engineClock = stable_pstate_sclk; in vega10_apply_state_adjust_rules()3267 if (sclk < minimum_clocks.engineClock) in vega10_apply_state_adjust_rules()3268 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in vega10_apply_state_adjust_rules()3269 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()4638 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_print_clock_levels()[all …]
799 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in smu7_setup_dpm_tables_v1()800 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()2608 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()2953 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()2976 minimum_clocks.engineClock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()3000 if (sclk < minimum_clocks.engineClock) in smu7_apply_state_adjust_rules()3001 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()3002 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()4568 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in smu7_print_clock_levels()4869 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in smu7_check_clk_voltage_valid()[all …]
1121 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()1159 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()1179 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
327 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()330 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
549 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu10_hwmgr_backend_init()
864 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
427 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
469 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega20_hwmgr_backend_init()
327 uint32_t engineClock; member
802 unsigned int engineClock; member
3010 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; in get_clock_requirements_for_state()
