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Searched refs:dpp_base (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
122 dpp1_power_on_degamma_lut(dpp_base, true); in dpp2_set_degamma_pwl()
123 dpp2_enable_cm_block(dpp_base); in dpp2_set_degamma_pwl()
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Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
76 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
96 struct dpp *dpp_base, in dpp2_cnv_setup() argument
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
238 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); in dpp2_cnv_setup()
240 dpp2_program_input_csc(dpp_base, color_space, select, NULL); in dpp2_cnv_setup()
249 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
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Ddcn20_hwseq.c841 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut() local
851 &dpp_base->regamma_params, false); in dcn20_set_blend_lut()
852 blend_lut = &dpp_base->regamma_params; in dcn20_set_blend_lut()
855 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn20_set_blend_lut()
863 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut() local
873 &dpp_base->shaper_params, true); in dcn20_set_shaper_3dlut()
874 shaper_lut = &dpp_base->shaper_params; in dcn20_set_shaper_3dlut()
878 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); in dcn20_set_shaper_3dlut()
881 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
884 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
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Ddcn20_dpp.h711 void dpp20_read_state(struct dpp *dpp_base,
715 struct dpp *dpp_base,
719 struct dpp *dpp_base,
723 struct dpp *dpp_base,
727 struct dpp *dpp_base,
733 struct dpp *dpp_base, const struct pwl_params *params);
736 struct dpp *dpp_base,
740 struct dpp *dpp_base,
744 struct dpp *dpp_base,
754 struct dpp *dpp_base,
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap()
240 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
243 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default()
310 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
313 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment()
318 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() argument
321 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut()
328 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, in dpp1_cm_program_regamma_lut() argument
333 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_program_regamma_lut()
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Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
196 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
198 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_reset()
212 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) in dpp1_cm_set_regamma_pwl() argument
214 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_regamma_pwl()
232 dpp1_cm_power_on_regamma_lut(dpp_base, true); in dpp1_cm_set_regamma_pwl()
233 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); in dpp1_cm_set_regamma_pwl()
236 dpp1_cm_program_regamma_luta_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
238 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
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Ddcn10_dpp_dscl.c168 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
525 struct dpp *dpp_base, in dpp1_dscl_set_scaler_auto_scale() argument
529 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_auto_scale()
531 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_auto_scale()
664 struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
668 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
670 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
Ddcn10_dpp.h1370 struct dpp *dpp_base,
1374 struct dpp *dpp_base,
1381 struct dpp *dpp_base,
1396 struct dpp *dpp_base,
1400 struct dpp *dpp_base,
1404 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1414 struct dpp *dpp_base,
1418 struct dpp *dpp_base,
1424 struct dpp *dpp_base,
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Ddcn10_hw_sequencer.c1577 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn10_set_input_transfer_func() local
1581 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
1588 !dpp_base->ctx->dc->debug.always_use_regamma in dcn10_set_input_transfer_func()
1591 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); in dcn10_set_input_transfer_func()
1594 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1598 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
1601 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
1604 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1607 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); in dcn10_set_input_transfer_func()
1608 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c44 void dpp30_read_state(struct dpp *dpp_base, in dpp30_read_state() argument
47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp30_read_state()
56 struct dpp *dpp_base, in dpp3_program_post_csc() argument
61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc()
129 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) in dpp3_set_pre_degam() argument
131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_pre_degam()
172 struct dpp *dpp_base, in dpp3_cnv_setup() argument
179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_cnv_setup()
332 dpp3_program_post_csc(dpp_base, color_space, select, in dpp3_cnv_setup()
335 dpp3_program_post_csc(dpp_base, color_space, select, NULL); in dpp3_cnv_setup()
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Ddcn30_dpp_cm.c44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block()
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current() argument
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current()
84 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
90 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut()
133 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
137 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_gamcor_lut()
151 struct dpp *dpp_base, in dpp3_program_cm_dealpha() argument
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Ddcn30_hwseq.c72 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut() local
81 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
82 blend_lut = &dpp_base->regamma_params; in dcn30_set_blend_lut()
85 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
93 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut() local
108 &dpp_base->shaper_params, true); in dcn30_set_mpc_shaper_3dlut()
109 shaper_lut = &dpp_base->shaper_params; in dcn30_set_mpc_shaper_3dlut()
147 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func() local
152 if (dpp_base == NULL || plane_state == NULL) in dcn30_set_input_transfer_func()
161 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
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Ddcn30_dpp.h569 struct dpp *dpp_base, const struct pwl_params *params);
572 struct dpp *dpp_base,
576 struct dpp *dpp_base,
580 struct dpp *dpp_base,
584 struct dpp *dpp_base,
587 void dpp3_set_pre_degam(struct dpp *dpp_base,
591 struct dpp *dpp_base,
595 struct dpp *dpp_base,
601 struct dpp *dpp_base,
605 struct dpp *dpp_base,
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddpp.h126 struct dpp *dpp_base, const struct pwl_params *params);
128 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
132 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
136 struct dpp *dpp_base,
199 struct dpp *dpp_base,
203 struct dpp *dpp_base,
206 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
210 struct dpp *dpp_base,
217 void (*dpp_full_bypass)(struct dpp *dpp_base);
220 struct dpp *dpp_base,
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