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/Linux-v5.10/drivers/gpu/drm/radeon/
Drv740_dpm.c124 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
137 engine_clock, false, &dividers); in rv740_populate_sclk_value()
141 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
199 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
205 memory_clock, false, &dividers); in rv740_populate_mclk_value()
209 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
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Drv730_dpm.c44 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
57 engine_clock, false, &dividers); in rv730_populate_sclk_value()
61 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
63 if (dividers.enable_post_div) in rv730_populate_sclk_value()
64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
74 if (dividers.enable_post_div) in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
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Drv6xx_dpm.c142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, &dividers); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) { in rv6xx_program_engine_spread_spectrum()
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers, in rv6xx_program_engine_spread_spectrum()
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Drv770_dpm.c320 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
332 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
333 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
402 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
410 memory_clock, false, &dividers); in rv770_populate_mclk_value()
414 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
419 &dividers, &clkf, &clkfrac); in rv770_populate_mclk_value()
421 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
432 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
438 if (dividers.vco_mode) in rv770_populate_mclk_value()
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Dcypress_dpm.c495 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
502 memory_clock, strobe_mode, &dividers); in cypress_populate_mclk_value()
510 dividers.post_div = 1; in cypress_populate_mclk_value()
513 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
522 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
523 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
526 if (dividers.vco_mode) in cypress_populate_mclk_value()
537 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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Drs780_dpm.c78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, &dividers); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1034 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1045 ps->sclk_high, false, &dividers); in rs780_dpm_force_performance_level()
1049 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1052 ps->sclk_low, false, &dividers); in rs780_dpm_force_performance_level()
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Dradeon_atombios.c2831 struct atom_clock_dividers *dividers) in radeon_atom_get_clock_dividers() argument
2838 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in radeon_atom_get_clock_dividers()
2851 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2852 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2853 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2865 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2866 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2867 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2869 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()
2871 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()
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/Linux-v5.10/drivers/gpu/drm/amd/display/modules/color/
Dcolor_gamma.c276 struct dividers { struct
1113 struct dividers dividers) in scale_gamma() argument
1149 dividers.divider1); in scale_gamma()
1151 dividers.divider1); in scale_gamma()
1153 dividers.divider1); in scale_gamma()
1158 dividers.divider2); in scale_gamma()
1160 dividers.divider2); in scale_gamma()
1162 dividers.divider2); in scale_gamma()
1167 dividers.divider3); in scale_gamma()
1169 dividers.divider3); in scale_gamma()
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/Linux-v5.10/drivers/clk/baikal-t1/
DKconfig12 configurable and fixed clock dividers. Enable this option to be able
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
36 Enable this to support the CCU dividers used to distribute clocks
38 SoC. CCU dividers can be either configurable or with fixed divider,
39 either gateable or ungateable. Some of the CCU dividers can be as well
/Linux-v5.10/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt30 Additionally an array of valid dividers may be supplied like so:
32 ti,dividers = <4>, <8>, <0>, <16>;
45 unless the divider array is provided, min and max dividers. Optionally
63 - ti,dividers : array of integers defining divisors
68 if ti,dividers is not defined.
70 only valid if ti,dividers is not defined.
72 only valid if ti,dividers is not defined.
116 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dppatomctrl.c350 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong() argument
363 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
364 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
373 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi() argument
387 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
389 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
392 dividers->ul_fb_div.ul_fb_div_frac = in atomctrl_get_engine_pll_dividers_vi()
394 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
397 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
399 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
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Dppatomctrl.h291 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
292 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
301 pp_atomctrl_clock_dividers_kong *dividers);
306 …dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
Dppatomfwctrl.c248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_atombios.c1000 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers() argument
1007 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1024 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1026 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1028 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1029 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1030 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1031 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1043 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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Damdgpu_atombios.h161 struct atom_clock_dividers *dividers);
214 struct atom_clock_dividers *dividers);
/Linux-v5.10/Documentation/devicetree/bindings/clock/
Ddove-divider-clock.txt3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
4 high speed clocks for a number of peripherals. These dividers are part of
Dbrcm,bcm2835-cprman.txt8 oscillator, a level of PLL dividers that produce channels off of the
12 the PLL dividers directly.
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c725 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
734 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers); in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
737 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
738 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
739 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
741 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
743 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
744 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
745 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in vegam_calculate_sclk_params()
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Dfiji_smumgr.c860 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
872 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers); in fiji_calculate_sclk_params()
880 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
883 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
887 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
889 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
903 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
932 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in fiji_calculate_sclk_params()
1304 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acpi_level() local
1335 table->ACPILevel.SclkFrequency, &dividers); in fiji_populate_smc_acpi_level()
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Dpolaris10_smumgr.c847 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
856 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers); in polaris10_calculate_sclk_params()
858 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
859 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
860 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
861 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
863 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
865 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
866 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
867 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in polaris10_calculate_sclk_params()
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Dci_smumgr.c300 struct pp_atomctrl_clock_dividers_vi dividers; in ci_calculate_sclk_params() local
312 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers); in ci_calculate_sclk_params()
320 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()
323 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
327 SPLL_REF_DIV, dividers.uc_pll_ref_div); in ci_calculate_sclk_params()
329 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
342 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()
365 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in ci_calculate_sclk_params()
1381 struct pp_atomctrl_clock_dividers_vi dividers; in ci_populate_smc_acpi_level() local
1404 table->ACPILevel.SclkFrequency, &dividers); in ci_populate_smc_acpi_level()
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Dtonga_smumgr.c542 pp_atomctrl_clock_dividers_vi dividers; in tonga_calculate_sclk_params() local
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers); in tonga_calculate_sclk_params()
562 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in tonga_calculate_sclk_params()
569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
611 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in tonga_calculate_sclk_params()
1180 struct pp_atomctrl_clock_dividers_vi dividers; in tonga_populate_smc_acpi_level() local
1199 table->ACPILevel.SclkFrequency, &dividers); in tonga_populate_smc_acpi_level()
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/Linux-v5.10/arch/arm/boot/dts/
Domap2420-clocks.dtsi79 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
262 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
266 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
Domap446x-clocks.dtsi14 ti,dividers = <8>, <16>, <32>;
/Linux-v5.10/Documentation/arm/samsung-s3c24xx/
Dcpufreq.rst16 PLL to feed the ARM, memory and peripherals via a series of dividers
27 system. Each CPU registers a driver to control the PLL, clock dividers

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