Searched refs:dfixed_const (Results 1 – 15 of 15) sorted by relevance
81 tmp.full = dfixed_const(100); in rs690_pm_info()82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); in rs690_pm_info()85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); in rs690_pm_info()87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); in rs690_pm_info()90 rdev->pm.igp_system_mclk.full = dfixed_const(400); in rs690_pm_info()91 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); in rs690_pm_info()92 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); in rs690_pm_info()95 tmp.full = dfixed_const(100); in rs690_pm_info()96 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); in rs690_pm_info()99 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); in rs690_pm_info()[all …]
981 a.full = dfixed_const(100); in rv515_crtc_bandwidth_compute()982 sclk.full = dfixed_const(selected_sclk); in rv515_crtc_bandwidth_compute()985 if (crtc->vsc.full > dfixed_const(2)) in rv515_crtc_bandwidth_compute()986 wm->num_line_pair.full = dfixed_const(2); in rv515_crtc_bandwidth_compute()988 wm->num_line_pair.full = dfixed_const(1); in rv515_crtc_bandwidth_compute()990 b.full = dfixed_const(mode->crtc_hdisplay); in rv515_crtc_bandwidth_compute()991 c.full = dfixed_const(256); in rv515_crtc_bandwidth_compute()995 if (a.full < dfixed_const(4)) { in rv515_crtc_bandwidth_compute()1007 a.full = dfixed_const(mode->clock); in rv515_crtc_bandwidth_compute()1008 b.full = dfixed_const(1000); in rv515_crtc_bandwidth_compute()[all …]
1954 a.full = dfixed_const(1000); in evergreen_dram_bandwidth()1955 yclk.full = dfixed_const(wm->yclk); in evergreen_dram_bandwidth()1957 dram_channels.full = dfixed_const(wm->dram_channels * 4); in evergreen_dram_bandwidth()1958 a.full = dfixed_const(10); in evergreen_dram_bandwidth()1959 dram_efficiency.full = dfixed_const(7); in evergreen_dram_bandwidth()1974 a.full = dfixed_const(1000); in evergreen_dram_bandwidth_for_display()1975 yclk.full = dfixed_const(wm->yclk); in evergreen_dram_bandwidth_for_display()1977 dram_channels.full = dfixed_const(wm->dram_channels * 4); in evergreen_dram_bandwidth_for_display()1978 a.full = dfixed_const(10); in evergreen_dram_bandwidth_for_display()1979 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in evergreen_dram_bandwidth_for_display()[all …]
2080 a.full = dfixed_const(1000); in dce6_dram_bandwidth()2081 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth()2083 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth()2084 a.full = dfixed_const(10); in dce6_dram_bandwidth()2085 dram_efficiency.full = dfixed_const(7); in dce6_dram_bandwidth()2100 a.full = dfixed_const(1000); in dce6_dram_bandwidth_for_display()2101 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth_for_display()2103 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth_for_display()2104 a.full = dfixed_const(10); in dce6_dram_bandwidth_for_display()2105 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce6_dram_bandwidth_for_display()[all …]
3265 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()3272 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()3273 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()3275 temp_ff.full = dfixed_const(pixel_bytes1); in r100_bandwidth_update()3279 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()3280 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ in r100_bandwidth_update()3282 temp_ff.full = dfixed_const(pixel_bytes2); in r100_bandwidth_update()3328 trcd_ff.full = dfixed_const(mem_trcd); in r100_bandwidth_update()3329 trp_ff.full = dfixed_const(mem_trp); in r100_bandwidth_update()3330 tras_ff.full = dfixed_const(mem_tras); in r100_bandwidth_update()[all …]
8947 a.full = dfixed_const(1000); in dce8_dram_bandwidth()8948 yclk.full = dfixed_const(wm->yclk); in dce8_dram_bandwidth()8950 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce8_dram_bandwidth()8951 a.full = dfixed_const(10); in dce8_dram_bandwidth()8952 dram_efficiency.full = dfixed_const(7); in dce8_dram_bandwidth()8976 a.full = dfixed_const(1000); in dce8_dram_bandwidth_for_display()8977 yclk.full = dfixed_const(wm->yclk); in dce8_dram_bandwidth_for_display()8979 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce8_dram_bandwidth_for_display()8980 a.full = dfixed_const(10); in dce8_dram_bandwidth_for_display()8981 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce8_dram_bandwidth_for_display()[all …]
1763 a.full = dfixed_const(src_v); in radeon_crtc_scaling_mode_fixup()1764 b.full = dfixed_const(dst_v); in radeon_crtc_scaling_mode_fixup()1766 a.full = dfixed_const(src_h); in radeon_crtc_scaling_mode_fixup()1767 b.full = dfixed_const(dst_h); in radeon_crtc_scaling_mode_fixup()1770 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()1771 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
730 a.full = dfixed_const(100); in radeon_update_bandwidth_info()731 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()733 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()737 a.full = dfixed_const(16); in radeon_update_bandwidth_info()
35 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ macro40 #define dfixed_init(A) { .full = dfixed_const((A)) }49 return dfixed_const(non_frac); in dfixed_floor()56 if (A.full > dfixed_const(non_frac)) in dfixed_ceil()57 return dfixed_const(non_frac + 1); in dfixed_ceil()59 return dfixed_const(non_frac); in dfixed_ceil()
525 a.full = dfixed_const(1000); in dce_v6_0_dram_bandwidth()526 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()528 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()529 a.full = dfixed_const(10); in dce_v6_0_dram_bandwidth()530 dram_efficiency.full = dfixed_const(7); in dce_v6_0_dram_bandwidth()554 a.full = dfixed_const(1000); in dce_v6_0_dram_bandwidth_for_display()555 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()557 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()558 a.full = dfixed_const(10); in dce_v6_0_dram_bandwidth_for_display()559 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v6_0_dram_bandwidth_for_display()[all …]
662 a.full = dfixed_const(1000); in dce_v8_0_dram_bandwidth()663 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth()665 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth()666 a.full = dfixed_const(10); in dce_v8_0_dram_bandwidth()667 dram_efficiency.full = dfixed_const(7); in dce_v8_0_dram_bandwidth()691 a.full = dfixed_const(1000); in dce_v8_0_dram_bandwidth_for_display()692 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth_for_display()694 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth_for_display()695 a.full = dfixed_const(10); in dce_v8_0_dram_bandwidth_for_display()696 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v8_0_dram_bandwidth_for_display()[all …]
727 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth()728 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()730 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()731 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth()732 dram_efficiency.full = dfixed_const(7); in dce_v10_0_dram_bandwidth()756 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth_for_display()757 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()759 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()760 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth_for_display()761 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v10_0_dram_bandwidth_for_display()[all …]
753 a.full = dfixed_const(1000); in dce_v11_0_dram_bandwidth()754 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth()756 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth()757 a.full = dfixed_const(10); in dce_v11_0_dram_bandwidth()758 dram_efficiency.full = dfixed_const(7); in dce_v11_0_dram_bandwidth()782 a.full = dfixed_const(1000); in dce_v11_0_dram_bandwidth_for_display()783 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth_for_display()785 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth_for_display()786 a.full = dfixed_const(10); in dce_v11_0_dram_bandwidth_for_display()787 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v11_0_dram_bandwidth_for_display()[all …]
757 a.full = dfixed_const(src_v); in amdgpu_display_crtc_scaling_mode_fixup()758 b.full = dfixed_const(dst_v); in amdgpu_display_crtc_scaling_mode_fixup()760 a.full = dfixed_const(src_h); in amdgpu_display_crtc_scaling_mode_fixup()761 b.full = dfixed_const(dst_h); in amdgpu_display_crtc_scaling_mode_fixup()764 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()765 amdgpu_crtc->hsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()146 inf.full -= dfixed_const(1); in compute_dda_inc()149 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); in compute_dda_inc()
